tinyriscv/rtl/perips
liangkangnan b0c4d1fa4d rtl:timer: update interrupt assert
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-07-12 22:33:15 +08:00
..
gpio.v gpio: add input function 2020-06-14 10:40:25 +08:00
ram.v use = instead of <= in combination logic 2020-05-02 11:57:25 +08:00
rom.v use = instead of <= in combination logic 2020-05-02 11:57:25 +08:00
spi.v perips: add spi master 2020-05-05 18:31:08 +08:00
timer.v rtl:timer: update interrupt assert 2020-07-12 22:33:15 +08:00
uart.v rtl: add uart rx function 2020-06-26 22:40:44 +08:00