66 lines
2.1 KiB
Systemverilog
66 lines
2.1 KiB
Systemverilog
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// 从多个master之间选择一个
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module obi_interconnect_master_sel #(
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parameter int unsigned MASTERS = 3,
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parameter MASTER_BITS = MASTERS == 1 ? 1 : $clog2(MASTERS)
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic master_req_i [MASTERS],
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input logic [ 31:0] master_addr_i [MASTERS],
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input logic [ 31:0] slave_addr_mask_i,
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input logic [ 31:0] slave_addr_base_i,
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output logic [MASTER_BITS-1:0] master_sel_int_o,
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output logic [MASTERS-1:0] master_sel_vec_o,
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output logic granted_master_o
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);
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function integer onehot2int;
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input [MASTERS-1:0] onehot;
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integer i;
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onehot2int = 0; // prevent latch behavior
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for (i = 1; i < MASTERS; i = i + 1) begin: gen_int
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if (onehot[i]) begin
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onehot2int = i;
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end
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end
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endfunction
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genvar m;
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logic[MASTERS-1:0] master_req;
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generate
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for (m = 0; m < MASTERS; m = m + 1) begin: gen_master_req_vec
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assign master_req[m] = master_req_i[m];
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end
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endgenerate
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logic[MASTERS-1:0] master_req_vec;
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logic[MASTERS-1:0] master_sel_vec;
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generate
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// 优先级仲裁机制，LSB优先级最高，MSB优先级最低
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for (m = 0; m < MASTERS; m = m + 1) begin: gen_master_sel_vec
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if (m == 0) begin: m_is_0
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assign master_req_vec[m] = 1'b1;
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end else begin: m_is_not_0
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assign master_req_vec[m] = ~(|master_req[m-1:0]);
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end
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assign master_sel_vec[m] = master_req_vec[m] &
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master_req_i[m] &
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((master_addr_i[m] & slave_addr_mask_i) == slave_addr_base_i);
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end
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endgenerate
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assign master_sel_int_o = onehot2int(master_sel_vec);
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assign master_sel_vec_o = master_sel_vec;
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assign granted_master_o = |master_sel_vec;
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endmodule
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