tinyriscv/rtl/utils
liangkangnan f74f2d8f5d rtl:utils:edge_detect: add DP parameter
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-09-01 14:14:36 +08:00
..
cdc_2phase.sv temp commit 2021-04-29 19:27:25 +08:00
clk_div.sv rtl: perips: rewrite uart module 2021-08-07 14:28:46 +08:00
edge_detect.sv rtl:utils:edge_detect: add DP parameter 2021-09-01 14:14:36 +08:00
gen_buf.sv rtl:utils:gen_buf: add handle for DP=0 2021-09-01 14:12:21 +08:00
gen_dff.sv temp commit 2021-04-25 17:14:09 +08:00
gen_ram.sv temp commit 2021-04-25 17:14:09 +08:00
prim_filter.sv rtl:perips: rewrite gpio 2021-08-13 09:33:15 +08:00
prim_subreg.sv rtl: perips: rewrite uart module 2021-08-07 14:28:46 +08:00
prim_subreg_arb.sv rtl: perips: rewrite uart module 2021-08-07 14:28:46 +08:00
prim_subreg_ext.sv rtl: perips: rewrite uart module 2021-08-07 14:28:46 +08:00
sync_fifo.sv rtl: add sync_fifo module 2021-06-28 11:09:37 +08:00