197 lines
7.8 KiB
Systemverilog
197 lines
7.8 KiB
Systemverilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 除法模块
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// 试商法实现32位整数除法
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// 每次除法运算至少需要33个时钟周期才能完成
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module divider(
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input wire clk,
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input wire rst_n,
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input wire[31:0] dividend_i, // 被除数
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input wire[31:0] divisor_i, // 除数
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input wire start_i, // 开始信号，运算期间这个信号需要一直保持有效
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input wire[3:0] op_i, // 具体是哪一条指令
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output reg[31:0] result_o, // 除法结果
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output reg ready_o // 运算结束信号
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);
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// 状态定义
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localparam STATE_IDLE = 4'b0001;
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localparam STATE_START = 4'b0010;
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localparam STATE_CALC = 4'b0100;
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localparam STATE_END = 4'b1000;
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reg[31:0] dividend_r;
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reg[31:0] divisor_r;
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reg[3:0] op_r;
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reg[3:0] state;
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reg[31:0] count;
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reg[31:0] div_result;
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reg[31:0] div_remain;
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reg[31:0] minuend;
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reg invert_result;
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wire op_div = op_r[3];
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wire op_divu = op_r[2];
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wire op_rem = op_r[1];
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wire op_remu = op_r[0];
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wire[31:0] dividend_invert = (-dividend_r);
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wire[31:0] divisor_invert = (-divisor_r);
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wire minuend_ge_divisor = minuend >= divisor_r;
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wire[31:0] minuend_sub_res = minuend - divisor_r;
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wire[31:0] div_result_tmp = minuend_ge_divisor? ({div_result[30:0], 1'b1}): ({div_result[30:0], 1'b0});
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wire[31:0] minuend_tmp = minuend_ge_divisor? minuend_sub_res[30:0]: minuend[30:0];
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// 状态机实现
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= STATE_IDLE;
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ready_o <= 1'b0;
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result_o <= 32'h0;
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div_result <= 32'h0;
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div_remain <= 32'h0;
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op_r <= 3'h0;
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dividend_r <= 32'h0;
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divisor_r <= 32'h0;
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minuend <= 32'h0;
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invert_result <= 1'b0;
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count <= 32'h0;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (start_i) begin
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op_r <= op_i;
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dividend_r <= dividend_i;
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divisor_r <= divisor_i;
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state <= STATE_START;
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end else begin
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op_r <= 3'h0;
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dividend_r <= 32'h0;
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divisor_r <= 32'h0;
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ready_o <= 1'b0;
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result_o <= 32'h0;
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end
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end
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STATE_START: begin
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if (start_i) begin
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// 除数为0
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if (divisor_r == 32'h0) begin
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if (op_div | op_divu) begin
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result_o <= 32'hffffffff;
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end else begin
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result_o <= dividend_r;
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end
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ready_o <= 1'b1;
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state <= STATE_IDLE;
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// 除数不为0
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end else begin
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count <= 32'h40000000;
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state <= STATE_CALC;
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div_result <= 32'h0;
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div_remain <= 32'h0;
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// DIV和REM这两条指令是有符号数运算指令
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if (op_div | op_rem) begin
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// 被除数求补码
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if (dividend_r[31] == 1'b1) begin
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dividend_r <= dividend_invert;
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minuend <= dividend_invert[31];
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end else begin
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minuend <= dividend_r[31];
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end
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// 除数求补码
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if (divisor_r[31] == 1'b1) begin
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divisor_r <= divisor_invert;
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end
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end else begin
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minuend <= dividend_r[31];
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end
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// 运算结束后是否要对结果取补码
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if ((op_div && (dividend_r[31] ^ divisor_r[31] == 1'b1))
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|| (op_rem && (dividend_r[31] == 1'b1))) begin
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invert_result <= 1'b1;
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end else begin
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invert_result <= 1'b0;
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end
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end
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end else begin
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state <= STATE_IDLE;
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result_o <= 32'h0;
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ready_o <= 1'b0;
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end
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end
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STATE_CALC: begin
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if (start_i) begin
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dividend_r <= {dividend_r[30:0], 1'b0};
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div_result <= div_result_tmp;
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count <= {1'b0, count[31:1]};
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if (|count) begin
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minuend <= {minuend_tmp[30:0], dividend_r[30]};
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end else begin
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state <= STATE_END;
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if (minuend_ge_divisor) begin
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div_remain <= minuend_sub_res;
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end else begin
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div_remain <= minuend;
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end
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end
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end else begin
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state <= STATE_IDLE;
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result_o <= 32'h0;
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ready_o <= 1'b0;
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end
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end
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STATE_END: begin
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if (start_i) begin
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ready_o <= 1'b1;
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state <= STATE_IDLE;
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if (op_div | op_divu) begin
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if (invert_result) begin
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result_o <= (-div_result);
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end else begin
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result_o <= div_result;
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end
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end else begin
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if (invert_result) begin
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result_o <= (-div_remain);
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end else begin
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result_o <= div_remain;
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end
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end
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end else begin
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state <= STATE_IDLE;
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result_o <= 32'h0;
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ready_o <= 1'b0;
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end
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end
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endcase
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end
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end
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endmodule
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