80 lines
2.7 KiB
Systemverilog
80 lines
2.7 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`define REG_CTRL 0
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`define REG_PRINT 4
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`define REG_DUMP 8
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module sim_ctrl(
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input logic clk_i,
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input logic rst_ni,
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output logic dump_wave_en_o,
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input logic req_i,
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output logic gnt_o,
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input logic[31:0] addr_i,
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input logic we_i,
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input logic[3:0] be_i,
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input logic[31:0] wdata_i,
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output logic rvalid_o,
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output logic[31:0] rdata_o
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);
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logic[7:0] reg_addr;
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assign reg_addr = {addr_i[7:2], 2'b0};
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assign gnt_o = req_i;
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assign rdata_o = 32'h0;
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always_ff @ (posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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dump_wave_en_o <= 1'b0;
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rvalid_o <= 1'b0;
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end else begin
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rvalid_o <= req_i;
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if (req_i & we_i) begin
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case (reg_addr)
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`REG_CTRL: begin
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if (be_i[0] & wdata_i[0]) begin
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$display("sim finish...");
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$finish;
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end
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end
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`REG_PRINT: begin
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if (be_i[0]) begin
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$display("%c", wdata_i[7:0]);
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end
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end
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`REG_DUMP: begin
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if (be_i[0] & wdata_i[0]) begin
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dump_wave_en_o <= 1'b1;
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end else if (be_i[0] & (!wdata_i[0])) begin
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dump_wave_en_o <= 1'b0;
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end
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end
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default: ;
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endcase
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end
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end
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end
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endmodule
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