tinyriscv/rtl
liangkangnan 4c16dfb254 rtl: move top module into fpga dir
Signed-off-by: liangkangnan <liangkangnan@163.com>
2022-08-10 08:13:38 +08:00
..
core rtl:core: ifu support for boot from flash 2021-11-25 09:00:09 +08:00
debug rtl🚌 use gnt and rvalid signal 2021-09-01 09:54:32 +08:00
perips rtl:perips:flash_ctrl: fix read state 2021-11-16 15:24:37 +08:00
sys_bus rtl🚌 use gnt and rvalid signal 2021-09-01 09:54:32 +08:00
utils rtl: utils: add up_counter module 2021-11-01 09:52:46 +08:00