345 lines
11 KiB
Verilog
345 lines
11 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// tinyriscv处理器核顶层模块
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module tinyriscv(
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input wire clk,
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input wire rst,
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output wire[`MemAddrBus] rib_ex_addr_o, // 读、写外设的地址
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input wire[`MemBus] rib_ex_data_i, // 从外设读取的数据
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output wire[`MemBus] rib_ex_data_o, // 写入外设的数据
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output wire rib_ex_req_o, // 访问外设请求
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output wire rib_ex_we_o, // 写外设标志
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output wire[`MemAddrBus] rib_pc_addr_o, // 取指地址
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input wire[`MemBus] rib_pc_data_i, // 取到的指令内容
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input wire[`RegAddrBus] jtag_reg_addr_i, // jtag模块读、写寄存器的地址
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input wire[`RegBus] jtag_reg_data_i, // jtag模块写寄存器数据
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input wire jtag_reg_we_i, // jtag模块写寄存器标志
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output wire[`RegBus] jtag_reg_data_o, // jtag模块读取到的寄存器数据
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input wire rib_hold_flag_i, // 总线暂停标志
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input wire jtag_halt_flag_i, // jtag暂停标志
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input wire jtag_reset_flag_i, // jtag复位PC标志
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input wire[`INT_BUS] int_i // 中断信号
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);
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// pc_reg模块输出信号
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wire[`InstAddrBus] pc_pc_o;
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// if_id模块输出信号
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wire[`InstBus] if_inst_o;
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wire[`InstAddrBus] if_inst_addr_o;
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// id模块输出信号
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wire[`RegAddrBus] id_reg1_raddr_o;
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wire[`RegAddrBus] id_reg2_raddr_o;
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wire id_mem_req_o;
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wire[`InstBus] id_inst_o;
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wire[`InstAddrBus] id_inst_addr_o;
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wire[`RegBus] id_reg1_rdata_o;
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wire[`RegBus] id_reg2_rdata_o;
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wire id_reg_we_o;
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wire[`RegAddrBus] id_reg_waddr_o;
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wire[`MemAddrBus] id_csr_raddr_o;
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wire id_csr_we_o;
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wire[`RegBus] id_csr_rdata_o;
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wire[`MemAddrBus] id_csr_waddr_o;
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// id_ex模块输出信号
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wire[`InstBus] ie_inst_o;
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wire[`InstAddrBus] ie_inst_addr_o;
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wire ie_reg_we_o;
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wire[`RegAddrBus] ie_reg_waddr_o;
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wire[`RegBus] ie_reg1_rdata_o;
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wire[`RegBus] ie_reg2_rdata_o;
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wire ie_csr_we_o;
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wire[`MemAddrBus] ie_csr_waddr_o;
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wire[`RegBus] ie_csr_rdata_o;
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// ex模块输出信号
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wire[`MemBus] ex_mem_wdata_o;
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wire[`MemAddrBus] ex_mem_raddr_o;
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wire[`MemAddrBus] ex_mem_waddr_o;
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wire ex_mem_we_o;
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wire ex_mem_req_o;
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wire[`RegBus] ex_reg_wdata_o;
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wire ex_reg_we_o;
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wire[`RegAddrBus] ex_reg_waddr_o;
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wire ex_hold_flag_o;
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wire ex_jump_flag_o;
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wire[`InstAddrBus] ex_jump_addr_o;
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wire ex_div_start_o;
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wire[`RegBus] ex_div_dividend_o;
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wire[`RegBus] ex_div_divisor_o;
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wire[2:0] ex_div_op_o;
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wire[`RegAddrBus] ex_div_reg_waddr_o;
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wire[`RegBus] ex_csr_wdata_o;
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wire ex_csr_we_o;
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wire[`MemAddrBus] ex_csr_waddr_o;
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// regs模块输出信号
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wire[`RegBus] regs_rdata1_o;
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wire[`RegBus] regs_rdata2_o;
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// csr_reg模块输出信号
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wire[`RegBus] csr_data_o;
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wire[`RegBus] csr_clint_data_o;
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wire csr_global_int_en_o;
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wire[`RegBus] csr_clint_csr_mtvec;
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wire[`RegBus] csr_clint_csr_mepc;
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wire[`RegBus] csr_clint_csr_mstatus;
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// ctrl模块输出信号
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wire[`Hold_Flag_Bus] ctrl_hold_flag_o;
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wire ctrl_jump_flag_o;
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wire[`InstAddrBus] ctrl_jump_addr_o;
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// div模块输出信号
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wire[`DoubleRegBus] div_result_o;
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wire div_ready_o;
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wire div_busy_o;
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wire[2:0] div_op_o;
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wire[`RegAddrBus] div_reg_waddr_o;
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// clint模块输出信号
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wire clint_we_o;
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wire[`MemAddrBus] clint_waddr_o;
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wire[`MemAddrBus] clint_raddr_o;
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wire[`RegBus] clint_data_o;
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wire[`InstAddrBus] clint_int_addr_o;
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wire clint_int_assert_o;
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wire clint_hold_flag_o;
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assign rib_ex_addr_o = (ex_mem_we_o == `WriteEnable)? ex_mem_waddr_o: ex_mem_raddr_o;
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assign rib_ex_data_o = ex_mem_wdata_o;
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assign rib_ex_req_o = ex_mem_req_o | id_mem_req_o;
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assign rib_ex_we_o = ex_mem_we_o;
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assign rib_pc_addr_o = pc_pc_o;
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// pc_reg模块例化
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pc_reg u_pc_reg(
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.clk(clk),
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.rst(rst),
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.jtag_reset_flag_i(jtag_reset_flag_i),
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.pc_o(pc_pc_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.jump_flag_i(ctrl_jump_flag_o),
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.jump_addr_i(ctrl_jump_addr_o)
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);
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// ctrl模块例化
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ctrl u_ctrl(
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.rst(rst),
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.jump_flag_i(ex_jump_flag_o),
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.jump_addr_i(ex_jump_addr_o),
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.hold_flag_ex_i(ex_hold_flag_o),
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.hold_flag_rib_i(rib_hold_flag_i),
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.hold_flag_o(ctrl_hold_flag_o),
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.hold_flag_clint_i(clint_hold_flag_o),
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.jump_flag_o(ctrl_jump_flag_o),
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.jump_addr_o(ctrl_jump_addr_o),
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.jtag_halt_flag_i(jtag_halt_flag_i)
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);
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// regs模块例化
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regs u_regs(
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.clk(clk),
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.rst(rst),
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.we_i(ex_reg_we_o),
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.waddr_i(ex_reg_waddr_o),
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.wdata_i(ex_reg_wdata_o),
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.raddr1_i(id_reg1_raddr_o),
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.rdata1_o(regs_rdata1_o),
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.raddr2_i(id_reg2_raddr_o),
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.rdata2_o(regs_rdata2_o),
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.jtag_we_i(jtag_reg_we_i),
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.jtag_addr_i(jtag_reg_addr_i),
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.jtag_data_i(jtag_reg_data_i),
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.jtag_data_o(jtag_reg_data_o)
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);
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// csr_reg模块例化
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csr_reg u_csr_reg(
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.clk(clk),
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.rst(rst),
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.we_i(ex_csr_we_o),
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.raddr_i(id_csr_raddr_o),
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.waddr_i(ex_csr_waddr_o),
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.data_i(ex_csr_wdata_o),
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.data_o(csr_data_o),
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.global_int_en_o(csr_global_int_en_o),
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.clint_we_i(clint_we_o),
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.clint_raddr_i(clint_raddr_o),
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.clint_waddr_i(clint_waddr_o),
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.clint_data_i(clint_data_o),
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.clint_data_o(csr_clint_data_o),
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.clint_csr_mtvec(csr_clint_csr_mtvec),
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.clint_csr_mepc(csr_clint_csr_mepc),
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.clint_csr_mstatus(csr_clint_csr_mstatus)
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);
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// if_id模块例化
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if_id u_if_id(
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.clk(clk),
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.rst(rst),
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.inst_i(rib_pc_data_i),
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.inst_addr_i(pc_pc_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.inst_o(if_inst_o),
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.inst_addr_o(if_inst_addr_o)
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);
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// id模块例化
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id u_id(
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.rst(rst),
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.inst_i(if_inst_o),
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.inst_addr_i(if_inst_addr_o),
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.reg1_rdata_i(regs_rdata1_o),
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.reg2_rdata_i(regs_rdata2_o),
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.ex_jump_flag_i(ex_jump_flag_o),
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.reg1_raddr_o(id_reg1_raddr_o),
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.reg2_raddr_o(id_reg2_raddr_o),
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.mem_req_o(id_mem_req_o),
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.inst_o(id_inst_o),
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.inst_addr_o(id_inst_addr_o),
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.reg1_rdata_o(id_reg1_rdata_o),
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.reg2_rdata_o(id_reg2_rdata_o),
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.reg_we_o(id_reg_we_o),
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.reg_waddr_o(id_reg_waddr_o),
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.csr_rdata_i(csr_data_o),
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.csr_raddr_o(id_csr_raddr_o),
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.csr_we_o(id_csr_we_o),
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.csr_rdata_o(id_csr_rdata_o),
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.csr_waddr_o(id_csr_waddr_o)
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);
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// id_ex模块例化
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id_ex u_id_ex(
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.clk(clk),
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.rst(rst),
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.inst_i(id_inst_o),
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.inst_addr_i(id_inst_addr_o),
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.reg_we_i(id_reg_we_o),
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.reg_waddr_i(id_reg_waddr_o),
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.reg1_rdata_i(id_reg1_rdata_o),
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.reg2_rdata_i(id_reg2_rdata_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.inst_o(ie_inst_o),
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.inst_addr_o(ie_inst_addr_o),
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.reg_we_o(ie_reg_we_o),
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.reg_waddr_o(ie_reg_waddr_o),
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.reg1_rdata_o(ie_reg1_rdata_o),
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.reg2_rdata_o(ie_reg2_rdata_o),
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.csr_we_i(id_csr_we_o),
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.csr_waddr_i(id_csr_waddr_o),
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.csr_rdata_i(id_csr_rdata_o),
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.csr_we_o(ie_csr_we_o),
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.csr_waddr_o(ie_csr_waddr_o),
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.csr_rdata_o(ie_csr_rdata_o)
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);
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// ex模块例化
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ex u_ex(
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.rst(rst),
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.inst_i(ie_inst_o),
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.inst_addr_i(ie_inst_addr_o),
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.reg_we_i(ie_reg_we_o),
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.reg_waddr_i(ie_reg_waddr_o),
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.reg1_rdata_i(ie_reg1_rdata_o),
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.reg2_rdata_i(ie_reg2_rdata_o),
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.mem_rdata_i(rib_ex_data_i),
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.mem_wdata_o(ex_mem_wdata_o),
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.mem_raddr_o(ex_mem_raddr_o),
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.mem_waddr_o(ex_mem_waddr_o),
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.mem_we_o(ex_mem_we_o),
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.mem_req_o(ex_mem_req_o),
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.reg_wdata_o(ex_reg_wdata_o),
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.reg_we_o(ex_reg_we_o),
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.reg_waddr_o(ex_reg_waddr_o),
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.hold_flag_o(ex_hold_flag_o),
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.jump_flag_o(ex_jump_flag_o),
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.jump_addr_o(ex_jump_addr_o),
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.int_assert_i(clint_int_assert_o),
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.int_addr_i(clint_int_addr_o),
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.div_ready_i(div_ready_o),
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.div_result_i(div_result_o),
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.div_busy_i(div_busy_o),
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.div_op_i(div_op_o),
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.div_reg_waddr_i(div_reg_waddr_o),
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.div_start_o(ex_div_start_o),
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.div_dividend_o(ex_div_dividend_o),
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.div_divisor_o(ex_div_divisor_o),
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.div_op_o(ex_div_op_o),
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.div_reg_waddr_o(ex_div_reg_waddr_o),
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.csr_we_i(ie_csr_we_o),
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.csr_waddr_i(ie_csr_waddr_o),
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.csr_rdata_i(ie_csr_rdata_o),
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.csr_wdata_o(ex_csr_wdata_o),
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.csr_we_o(ex_csr_we_o),
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.csr_waddr_o(ex_csr_waddr_o)
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);
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// div模块例化
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div u_div(
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.clk(clk),
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.rst(rst),
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.dividend_i(ex_div_dividend_o),
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.divisor_i(ex_div_divisor_o),
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.start_i(ex_div_start_o),
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.op_i(ex_div_op_o),
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.reg_waddr_i(ex_div_reg_waddr_o),
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.result_o(div_result_o),
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.ready_o(div_ready_o),
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.busy_o(div_busy_o),
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.op_o(div_op_o),
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.reg_waddr_o(div_reg_waddr_o)
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);
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// clint模块例化
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clint u_clint(
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.clk(clk),
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.rst(rst),
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.int_flag_i(int_i),
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.inst_i(id_inst_o),
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.inst_addr_i(id_inst_addr_o),
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.hold_flag_i(ctrl_hold_flag_o),
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.data_i(csr_clint_data_o),
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.csr_mtvec(csr_clint_csr_mtvec),
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.csr_mepc(csr_clint_csr_mepc),
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.csr_mstatus(csr_clint_csr_mstatus),
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.we_o(clint_we_o),
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.waddr_o(clint_waddr_o),
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.raddr_o(clint_raddr_o),
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.data_o(clint_data_o),
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.hold_flag_o(clint_hold_flag_o),
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.global_int_en_i(csr_global_int_en_o),
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.int_addr_o(clint_int_addr_o),
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.int_assert_o(clint_int_assert_o)
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);
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endmodule
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