215 lines
7.5 KiB
Verilog
215 lines
7.5 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// core local interruptor module
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// 核心中断管理、仲裁模块
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module clint(
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input wire clk,
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input wire rst,
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// from core
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input wire[`INT_BUS] int_flag_i, // 中断输入信号
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// from id
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input wire[`InstBus] inst_i, // 指令内容
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input wire[`InstAddrBus] inst_addr_i, // 指令地址
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// from ctrl
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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// from csr_reg
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input wire[`RegBus] data_i, // CSR寄存器输入数据
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input wire[`RegBus] csr_mtvec, // mtvec寄存器
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input wire[`RegBus] csr_mepc, // mepc寄存器
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input wire[`RegBus] csr_mstatus, // mstatus寄存器
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input wire global_int_en_i, // 全局中断使能标志
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// to ctrl
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output wire hold_flag_o, // 流水线暂停标志
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// to csr_reg
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output reg we_o, // 写CSR寄存器标志
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output reg[`MemAddrBus] waddr_o, // 写CSR寄存器地址
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output reg[`MemAddrBus] raddr_o, // 读CSR寄存器地址
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output reg[`RegBus] data_o, // 写CSR寄存器数据
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// to ex
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output reg[`InstAddrBus] int_addr_o, // 中断入口地址
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output reg int_assert_o // 中断标志
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);
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// 中断状态定义
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localparam S_INT_IDLE = 4'b0001;
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localparam S_INT_SYNC_ASSERT = 4'b0010;
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localparam S_INT_ASYNC_ASSERT = 4'b0100;
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localparam S_INT_MRET = 4'b1000;
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// 写CSR寄存器状态定义
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localparam S_CSR_IDLE = 5'b00001;
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localparam S_CSR_MSTATUS = 5'b00010;
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localparam S_CSR_MEPC = 5'b00100;
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localparam S_CSR_MSTATUS_MRET = 5'b01000;
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localparam S_CSR_MCAUSE = 5'b10000;
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reg[3:0] int_state;
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reg[4:0] csr_state;
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reg[`InstAddrBus] inst_addr;
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reg[31:0] cause;
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assign hold_flag_o = ((int_state != S_INT_IDLE) || (csr_state != S_CSR_IDLE))? `HoldEnable: `HoldDisable;
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// 中断仲裁逻辑
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always @ (*) begin
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if (rst == `RstEnable) begin
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int_state = S_INT_IDLE;
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end else begin
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if (inst_i == `INST_ECALL || inst_i == `INST_EBREAK) begin
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int_state = S_INT_SYNC_ASSERT;
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end else if (int_flag_i != `INT_NONE && global_int_en_i == `True) begin
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int_state = S_INT_ASYNC_ASSERT;
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end else if (inst_i == `INST_MRET) begin
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int_state = S_INT_MRET;
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end else begin
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int_state = S_INT_IDLE;
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end
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end
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end
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// 写CSR寄存器状态切换
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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csr_state <= S_CSR_IDLE;
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cause <= `ZeroWord;
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inst_addr <= `ZeroWord;
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end else begin
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case (csr_state)
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S_CSR_IDLE: begin
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if (int_state == S_INT_SYNC_ASSERT) begin
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csr_state <= S_CSR_MEPC;
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inst_addr <= inst_addr_i;
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case (inst_i)
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`INST_ECALL: begin
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cause <= 32'd11;
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end
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`INST_EBREAK: begin
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cause <= 32'd3;
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end
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default: begin
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cause <= 32'd10;
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end
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endcase
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end else if (int_state == S_INT_ASYNC_ASSERT) begin
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// 定时器中断
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cause <= 32'h80000004;
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csr_state <= S_CSR_MEPC;
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inst_addr <= inst_addr_i;
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// 中断返回
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end else if (int_state == S_INT_MRET) begin
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csr_state <= S_CSR_MSTATUS_MRET;
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end
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end
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S_CSR_MEPC: begin
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csr_state <= S_CSR_MCAUSE;
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end
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S_CSR_MCAUSE: begin
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csr_state <= S_CSR_MSTATUS;
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end
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S_CSR_MSTATUS: begin
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csr_state <= S_CSR_IDLE;
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end
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S_CSR_MSTATUS_MRET: begin
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csr_state <= S_CSR_IDLE;
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end
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default: begin
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csr_state <= S_CSR_IDLE;
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end
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endcase
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end
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end
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// 发出中断信号前，先写几个CSR寄存器
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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we_o <= `WriteDisable;
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waddr_o <= `ZeroWord;
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data_o <= `ZeroWord;
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end else begin
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case (csr_state)
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// 将mepc寄存器的值设为当前指令地址
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S_CSR_MEPC: begin
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we_o <= `WriteEnable;
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waddr_o <= {20'h0, `CSR_MEPC};
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data_o <= inst_addr;
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end
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// 写中断产生的原因
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S_CSR_MCAUSE: begin
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we_o <= `WriteEnable;
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waddr_o <= {20'h0, `CSR_MCAUSE};
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data_o <= cause;
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end
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// 关闭全局中断
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S_CSR_MSTATUS: begin
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we_o <= `WriteEnable;
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waddr_o <= {20'h0, `CSR_MSTATUS};
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data_o <= {csr_mstatus[31:4], 1'b0, csr_mstatus[2:0]};
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end
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// 中断返回
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S_CSR_MSTATUS_MRET: begin
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we_o <= `WriteEnable;
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waddr_o <= {20'h0, `CSR_MSTATUS};
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data_o <= {csr_mstatus[31:4], csr_mstatus[7], csr_mstatus[2:0]};
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end
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default: begin
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we_o <= `WriteDisable;
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waddr_o <= `ZeroWord;
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data_o <= `ZeroWord;
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end
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endcase
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end
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end
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// 发出中断信号给ex模块
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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int_assert_o <= `INT_DEASSERT;
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int_addr_o <= `ZeroWord;
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end else begin
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// 发出中断进入信号.写完mstatus寄存器才能发
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if (csr_state == S_CSR_MSTATUS) begin
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int_assert_o <= `INT_ASSERT;
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int_addr_o <= csr_mtvec;
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// 发出中断返回信号
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end else if (csr_state == S_CSR_MSTATUS_MRET) begin
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int_assert_o <= `INT_ASSERT;
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int_addr_o <= csr_mepc;
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end else begin
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int_assert_o <= `INT_DEASSERT;
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int_addr_o <= `ZeroWord;
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end
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end
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end
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endmodule
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