tinyriscv/rtl/core
liangkangnan a73b0ea36b rtl: add uart_debug module
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-07-04 14:32:31 +08:00
..
clint.v add support for ebreak inst 2020-06-13 14:56:44 +08:00
csr_reg.v rtl: core: fix data related for csr regs 2020-06-05 22:22:49 +08:00
ctrl.v use = instead of <= in combination logic 2020-05-02 11:58:44 +08:00
defines.v add support for ebreak inst 2020-06-13 14:56:44 +08:00
div.v stop div when interrupt assert 2020-04-25 17:04:44 +08:00
ex.v fix nop inst 2020-05-07 22:40:31 +08:00
id.v fix nop inst 2020-05-07 22:40:31 +08:00
id_ex.v add code comments 2020-04-18 20:14:37 +08:00
if_id.v add code comments 2020-04-18 20:14:37 +08:00
pc_reg.v add code comments 2020-04-18 20:14:37 +08:00
regs.v use = instead of <= 2020-05-31 14:38:57 +08:00
rib.v rtl: add uart_debug module 2020-07-04 14:32:31 +08:00
tinyriscv.v add signal 2020-04-25 17:15:46 +08:00