162 lines
4.2 KiB
Verilog
162 lines
4.2 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`define CpuResetAddr 32'h0
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`define RstEnable 1'b0
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`define RstDisable 1'b1
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`define ZeroWord 32'h0
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`define ZeroReg 5'h0
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`define WriteEnable 1'b1
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`define WriteDisable 1'b0
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`define ReadEnable 1'b1
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`define ReadDisable 1'b0
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`define True 1'b1
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`define False 1'b0
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`define ChipEnable 1'b1
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`define ChipDisable 1'b0
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`define JumpEnable 1'b1
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`define JumpDisable 1'b0
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`define DivResultNotReady 1'b0
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`define DivResultReady 1'b1
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`define DivStart 1'b1
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`define DivStop 1'b0
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`define HoldEnable 1'b1
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`define HoldDisable 1'b0
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`define Stop 1'b1
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`define NoStop 1'b0
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`define RIB_ACK 1'b1
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`define RIB_NACK 1'b0
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`define RIB_REQ 1'b1
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`define RIB_NREQ 1'b0
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`define INT_ASSERT 1'b1
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`define INT_DEASSERT 1'b0
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`define INT_BUS 7:0
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`define INT_NONE 8'h0
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`define INT_RET 8'hff
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`define INT_TIMER0 8'b00000001
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`define INT_TIMER0_ENTRY_ADDR 32'h4
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`define Hold_Flag_Bus 2:0
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`define Hold_None 3'b000
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`define Hold_Pc 3'b001
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`define Hold_If 3'b010
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`define Hold_Id 3'b011
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// I type inst
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`define INST_TYPE_I 7'b0010011
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`define INST_ADDI 3'b000
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`define INST_SLTI 3'b010
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`define INST_SLTIU 3'b011
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`define INST_XORI 3'b100
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`define INST_ORI 3'b110
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`define INST_ANDI 3'b111
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`define INST_SLLI 3'b001
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`define INST_SRI 3'b101
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// L type inst
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`define INST_TYPE_L 7'b0000011
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`define INST_LB 3'b000
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`define INST_LH 3'b001
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`define INST_LW 3'b010
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`define INST_LBU 3'b100
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`define INST_LHU 3'b101
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// S type inst
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`define INST_TYPE_S 7'b0100011
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`define INST_SB 3'b000
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`define INST_SH 3'b001
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`define INST_SW 3'b010
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// R and M type inst
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`define INST_TYPE_R_M 7'b0110011
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// R type inst
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`define INST_ADD_SUB 3'b000
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`define INST_SLL 3'b001
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`define INST_SLT 3'b010
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`define INST_SLTU 3'b011
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`define INST_XOR 3'b100
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`define INST_SR 3'b101
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`define INST_OR 3'b110
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`define INST_AND 3'b111
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// M type inst
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`define INST_MUL 3'b000
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`define INST_MULH 3'b001
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`define INST_MULHSU 3'b010
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`define INST_MULHU 3'b011
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`define INST_DIV 3'b100
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`define INST_DIVU 3'b101
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`define INST_REM 3'b110
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`define INST_REMU 3'b111
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// J type inst
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`define INST_JAL 7'b1101111
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`define INST_JALR 7'b1100111
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`define INST_LUI 7'b0110111
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`define INST_AUIPC 7'b0010111
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`define INST_NOP 32'h00000001
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`define INST_MRET 32'h30200073
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`define INST_RET 32'h00008067
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`define INST_FENCE 7'b0001111
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`define INST_ECALL 32'h73
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// J type inst
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`define INST_TYPE_B 7'b1100011
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`define INST_BEQ 3'b000
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`define INST_BNE 3'b001
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`define INST_BLT 3'b100
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`define INST_BGE 3'b101
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`define INST_BLTU 3'b110
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`define INST_BGEU 3'b111
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// CSR inst
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`define INST_CSR 7'b1110011
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`define INST_CSRRW 3'b001
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`define INST_CSRRS 3'b010
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`define INST_CSRRC 3'b011
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`define INST_CSRRWI 3'b101
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`define INST_CSRRSI 3'b110
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`define INST_CSRRCI 3'b111
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// CSR reg addr
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`define CSR_CYCLE 12'hc00
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`define CSR_CYCLEH 12'hc80
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`define CSR_MTVEC 12'h305
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`define CSR_MCAUSE 12'h342
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`define CSR_MEPC 12'h341
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`define CSR_MIE 12'h304
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`define CSR_MSTATUS 12'h300
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`define RomNum 4096 // rom depth(how many words)
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`define MemNum 4096 // memory depth(how many words)
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`define MemBus 31:0
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`define MemAddrBus 31:0
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`define InstBus 31:0
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`define InstAddrBus 31:0
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// common regs
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`define RegAddrBus 4:0
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`define RegBus 31:0
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`define DoubleRegBus 63:0
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`define RegWidth 32
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`define RegNum 32 // reg num
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`define RegNumLog2 5
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