466 lines
10 KiB
Systemverilog
466 lines
10 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Top module auto-generated by `reggen`
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module rvic_reg_top (
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input logic clk_i,
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input logic rst_ni,
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// To HW
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output rvic_reg_pkg::rvic_reg2hw_t reg2hw, // Write
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input rvic_reg_pkg::rvic_hw2reg_t hw2reg, // Read
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input logic reg_we,
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input logic reg_re,
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input logic [31:0] reg_wdata,
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input logic [ 3:0] reg_be,
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input logic [31:0] reg_addr,
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output logic [31:0] reg_rdata
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);
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import rvic_reg_pkg::* ;
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localparam int AW = 6;
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localparam int DW = 32;
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localparam int DBW = DW/8; // Byte Width
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logic reg_error;
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logic addrmiss, wr_err;
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logic [DW-1:0] reg_rdata_next;
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assign reg_rdata = reg_rdata_next;
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assign reg_error = wr_err;
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// Define SW related signals
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// Format: <reg>_<field>_{wd|we|qs}
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// or <reg>_{wd|we|qs} if field == 1 or 0
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logic enable_we;
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logic [31:0] enable_qs;
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logic [31:0] enable_wd;
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logic pending_we;
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logic [31:0] pending_qs;
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logic [31:0] pending_wd;
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logic priority0_we;
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logic [31:0] priority0_qs;
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logic [31:0] priority0_wd;
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logic priority1_we;
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logic [31:0] priority1_qs;
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logic [31:0] priority1_wd;
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logic priority2_we;
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logic [31:0] priority2_qs;
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logic [31:0] priority2_wd;
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logic priority3_we;
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logic [31:0] priority3_qs;
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logic [31:0] priority3_wd;
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logic priority4_we;
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logic [31:0] priority4_qs;
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logic [31:0] priority4_wd;
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logic priority5_we;
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logic [31:0] priority5_qs;
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logic [31:0] priority5_wd;
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logic priority6_we;
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logic [31:0] priority6_qs;
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logic [31:0] priority6_wd;
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logic priority7_we;
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logic [31:0] priority7_qs;
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logic [31:0] priority7_wd;
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// Register instances
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// R[enable]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_enable (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (enable_we),
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.wd (enable_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.enable.q),
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// to register interface (read)
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.qs (enable_qs)
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);
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// R[pending]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("W1C"),
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.RESVAL (32'h0)
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) u_pending (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (pending_we),
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.wd (pending_wd),
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// from internal hardware
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.de (hw2reg.pending.de),
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.d (hw2reg.pending.d),
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// to internal hardware
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.qe (),
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.q (reg2hw.pending.q),
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// to register interface (read)
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.qs (pending_qs)
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);
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// R[priority0]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority0 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority0_we),
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.wd (priority0_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority0.q),
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// to register interface (read)
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.qs (priority0_qs)
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);
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// R[priority1]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority1 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority1_we),
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.wd (priority1_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority1.q),
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// to register interface (read)
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.qs (priority1_qs)
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);
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// R[priority2]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority2 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority2_we),
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.wd (priority2_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority2.q),
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// to register interface (read)
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.qs (priority2_qs)
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);
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// R[priority3]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority3 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority3_we),
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.wd (priority3_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority3.q),
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// to register interface (read)
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.qs (priority3_qs)
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);
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// R[priority4]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority4 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority4_we),
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.wd (priority4_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority4.q),
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// to register interface (read)
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.qs (priority4_qs)
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);
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// R[priority5]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority5 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority5_we),
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.wd (priority5_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority5.q),
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// to register interface (read)
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.qs (priority5_qs)
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);
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// R[priority6]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority6 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority6_we),
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.wd (priority6_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority6.q),
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// to register interface (read)
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.qs (priority6_qs)
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);
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// R[priority7]: V(False)
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prim_subreg #(
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.DW (32),
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.SWACCESS("RW"),
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.RESVAL (32'h0)
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) u_priority7 (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (priority7_we),
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.wd (priority7_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (),
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.q (reg2hw.priority7.q),
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// to register interface (read)
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.qs (priority7_qs)
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);
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logic [9:0] addr_hit;
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always_comb begin
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addr_hit = '0;
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addr_hit[0] = (reg_addr == RVIC_ENABLE_OFFSET);
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addr_hit[1] = (reg_addr == RVIC_PENDING_OFFSET);
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addr_hit[2] = (reg_addr == RVIC_PRIORITY0_OFFSET);
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addr_hit[3] = (reg_addr == RVIC_PRIORITY1_OFFSET);
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addr_hit[4] = (reg_addr == RVIC_PRIORITY2_OFFSET);
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addr_hit[5] = (reg_addr == RVIC_PRIORITY3_OFFSET);
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addr_hit[6] = (reg_addr == RVIC_PRIORITY4_OFFSET);
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addr_hit[7] = (reg_addr == RVIC_PRIORITY5_OFFSET);
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addr_hit[8] = (reg_addr == RVIC_PRIORITY6_OFFSET);
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addr_hit[9] = (reg_addr == RVIC_PRIORITY7_OFFSET);
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end
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assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
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// Check sub-word write is permitted
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always_comb begin
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wr_err = (reg_we &
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((addr_hit[0] & (|(RVIC_PERMIT[0] & ~reg_be))) |
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(addr_hit[1] & (|(RVIC_PERMIT[1] & ~reg_be))) |
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(addr_hit[2] & (|(RVIC_PERMIT[2] & ~reg_be))) |
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(addr_hit[3] & (|(RVIC_PERMIT[3] & ~reg_be))) |
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(addr_hit[4] & (|(RVIC_PERMIT[4] & ~reg_be))) |
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(addr_hit[5] & (|(RVIC_PERMIT[5] & ~reg_be))) |
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(addr_hit[6] & (|(RVIC_PERMIT[6] & ~reg_be))) |
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(addr_hit[7] & (|(RVIC_PERMIT[7] & ~reg_be))) |
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(addr_hit[8] & (|(RVIC_PERMIT[8] & ~reg_be))) |
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(addr_hit[9] & (|(RVIC_PERMIT[9] & ~reg_be)))));
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end
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assign enable_we = addr_hit[0] & reg_we & !reg_error;
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assign enable_wd = reg_wdata[31:0];
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assign pending_we = addr_hit[1] & reg_we & !reg_error;
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assign pending_wd = reg_wdata[31:0];
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assign priority0_we = addr_hit[2] & reg_we & !reg_error;
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assign priority0_wd = reg_wdata[31:0];
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assign priority1_we = addr_hit[3] & reg_we & !reg_error;
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assign priority1_wd = reg_wdata[31:0];
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assign priority2_we = addr_hit[4] & reg_we & !reg_error;
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assign priority2_wd = reg_wdata[31:0];
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assign priority3_we = addr_hit[5] & reg_we & !reg_error;
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assign priority3_wd = reg_wdata[31:0];
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assign priority4_we = addr_hit[6] & reg_we & !reg_error;
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assign priority4_wd = reg_wdata[31:0];
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assign priority5_we = addr_hit[7] & reg_we & !reg_error;
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assign priority5_wd = reg_wdata[31:0];
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assign priority6_we = addr_hit[8] & reg_we & !reg_error;
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assign priority6_wd = reg_wdata[31:0];
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assign priority7_we = addr_hit[9] & reg_we & !reg_error;
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assign priority7_wd = reg_wdata[31:0];
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// Read data return
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always_comb begin
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reg_rdata_next = '0;
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unique case (1'b1)
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addr_hit[0]: begin
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reg_rdata_next[31:0] = enable_qs;
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end
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addr_hit[1]: begin
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reg_rdata_next[31:0] = pending_qs;
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end
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addr_hit[2]: begin
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reg_rdata_next[31:0] = priority0_qs;
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end
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addr_hit[3]: begin
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reg_rdata_next[31:0] = priority1_qs;
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end
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addr_hit[4]: begin
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reg_rdata_next[31:0] = priority2_qs;
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end
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addr_hit[5]: begin
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reg_rdata_next[31:0] = priority3_qs;
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end
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addr_hit[6]: begin
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reg_rdata_next[31:0] = priority4_qs;
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end
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addr_hit[7]: begin
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reg_rdata_next[31:0] = priority5_qs;
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end
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addr_hit[8]: begin
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reg_rdata_next[31:0] = priority6_qs;
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end
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addr_hit[9]: begin
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reg_rdata_next[31:0] = priority7_qs;
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end
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default: begin
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reg_rdata_next = '1;
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end
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endcase
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end
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// Unused signal tieoff
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// wdata / byte enable are not always fully used
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// add a blanket unused statement to handle lint waivers
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logic unused_wdata;
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logic unused_be;
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assign unused_wdata = ^reg_wdata;
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assign unused_be = ^reg_be;
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endmodule
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