353 lines
9.4 KiB
Systemverilog
353 lines
9.4 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// CSR寄存器模块
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module csr_reg(
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input wire clk,
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input wire rst_n,
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// exu
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input wire exu_we_i, // exu模块写寄存器标志
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input wire[31:0] exu_waddr_i, // exu模块写寄存器地址
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input wire[31:0] exu_wdata_i, // exu模块写寄存器数据
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input wire[31:0] exu_raddr_i, // exu模块读寄存器地址
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output wire[31:0] exu_rdata_o, // exu模块读寄存器数据
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// clint
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input wire clint_we_i, // clint模块写寄存器标志
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input wire[31:0] clint_waddr_i, // clint模块写寄存器地址
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input wire[31:0] clint_wdata_i, // clint模块写寄存器数据
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output wire[31:0] mtvec_o, // mtvec寄存器值
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output wire[31:0] mepc_o, // mepc寄存器值
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output wire[31:0] mstatus_o, // mstatus寄存器值
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output wire[31:0] mie_o, // mie寄存器值
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output wire[31:0] dpc_o, // dpc寄存器值
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output wire[31:0] dcsr_o // dcsr寄存器值
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);
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reg[31:0] mtvec_d;
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wire[31:0] mtvec_q;
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reg mtvec_we;
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reg[31:0] mcause_d;
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wire[31:0] mcause_q;
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reg mcause_we;
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reg[31:0] mepc_d;
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wire[31:0] mepc_q;
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reg mepc_we;
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reg[31:0] mie_d;
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wire[31:0] mie_q;
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reg mie_we;
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reg[31:0] mstatus_d;
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wire[31:0] mstatus_q;
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reg mstatus_we;
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reg[31:0] mscratch_d;
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wire[31:0] mscratch_q;
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reg mscratch_we;
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reg[31:0] dscratch0_d;
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wire[31:0] dscratch0_q;
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reg dscratch0_we;
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reg[31:0] dscratch1_d;
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wire[31:0] dscratch1_q;
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reg dscratch1_we;
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reg[31:0] mhartid_d;
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wire[31:0] mhartid_q;
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reg mhartid_we;
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reg[31:0] dpc_d;
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wire[31:0] dpc_q;
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reg dpc_we;
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reg[31:0] dcsr_d;
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wire[31:0] dcsr_q;
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reg dcsr_we;
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reg[63:0] cycle;
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// cycle counter
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// 复位撤销后就一直计数
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cycle <= {32'h0, 32'h0};
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end else begin
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cycle <= cycle + 1'b1;
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end
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end
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assign mtvec_o = mtvec_q;
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assign mepc_o = mepc_q;
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assign mstatus_o = mstatus_q;
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assign mie_o = mie_q;
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assign dpc_o = dpc_q;
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assign dcsr_o = dcsr_q;
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reg[31:0] exu_rdata;
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// exu模块读CSR寄存器
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always @ (*) begin
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case (exu_raddr_i[11:0])
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`CSR_CYCLE: begin
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exu_rdata = cycle[31:0];
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end
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`CSR_CYCLEH: begin
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exu_rdata = cycle[63:32];
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end
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`CSR_MTVEC: begin
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exu_rdata = mtvec_q;
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end
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`CSR_MCAUSE: begin
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exu_rdata = mcause_q;
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end
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`CSR_MEPC: begin
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exu_rdata = mepc_q;
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end
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`CSR_MIE: begin
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exu_rdata = mie_q;
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end
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`CSR_MSTATUS: begin
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exu_rdata = mstatus_q;
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end
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`CSR_MSCRATCH: begin
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exu_rdata = mscratch_q;
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end
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`CSR_DSCRATCH0: begin
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exu_rdata = dscratch0_q;
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end
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`CSR_DSCRATCH1: begin
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exu_rdata = dscratch1_q;
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end
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`CSR_MHARTID: begin
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exu_rdata = mhartid_q;
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end
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`CSR_DPC: begin
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exu_rdata = dpc_q;
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end
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`CSR_DCSR: begin
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exu_rdata = dcsr_q;
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end
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default: begin
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exu_rdata = 32'h0;
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end
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endcase
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end
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assign exu_rdata_o = exu_rdata;
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// 写CSR寄存器
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wire we = exu_we_i | clint_we_i;
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wire[31:0] waddr = exu_we_i? exu_waddr_i: clint_waddr_i;
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wire[31:0] wdata = exu_we_i? exu_wdata_i: clint_wdata_i;
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always @ (*) begin
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mtvec_d = mtvec_q;
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mtvec_we = 1'b0;
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mcause_d = mcause_q;
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mcause_we = 1'b0;
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mepc_d = mepc_q;
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mepc_we = 1'b0;
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mie_d = mie_q;
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mie_we = 1'b0;
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mstatus_d = mstatus_q;
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mstatus_we = 1'b0;
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mscratch_d = mscratch_q;
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mscratch_we = 1'b0;
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dscratch0_d = dscratch0_q;
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dscratch0_we = 1'b0;
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dscratch1_d = dscratch1_q;
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dscratch1_we = 1'b0;
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mhartid_d = mhartid_q;
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mhartid_we = 1'b0;
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dpc_d = dpc_q;
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dpc_we = 1'b0;
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dcsr_d = dcsr_q;
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dcsr_we = 1'b0;
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if (we) begin
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case (waddr[11:0])
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`CSR_MTVEC: begin
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mtvec_d = wdata;
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mtvec_we = 1'b1;
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end
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`CSR_MCAUSE: begin
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mcause_d = wdata;
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mcause_we = 1'b1;
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end
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`CSR_MEPC: begin
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mepc_d = wdata;
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mepc_we = 1'b1;
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end
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`CSR_MIE: begin
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mie_d = wdata;
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mie_we = 1'b1;
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end
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`CSR_MSTATUS: begin
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mstatus_d = wdata;
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mstatus_we = 1'b1;
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end
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`CSR_MSCRATCH: begin
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mscratch_d = wdata;
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mscratch_we = 1'b1;
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end
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`CSR_DSCRATCH0: begin
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dscratch0_d = wdata;
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dscratch0_we = 1'b1;
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end
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`CSR_DSCRATCH1: begin
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dscratch1_d = wdata;
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dscratch1_we = 1'b1;
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end
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`CSR_MHARTID: begin
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mhartid_d = wdata;
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mhartid_we = 1'b1;
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end
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`CSR_DPC: begin
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dpc_d = wdata;
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dpc_we = 1'b1;
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end
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`CSR_DCSR: begin
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dcsr_d = wdata;
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dcsr_we = 1'b1;
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end
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default:;
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endcase
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end
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end
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// mtvec
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csr #(
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.RESET_VAL(32'h0)
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) mtvec_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mtvec_d),
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.we_i(mtvec_we),
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.rdata_o(mtvec_q)
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);
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// mcause
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csr #(
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.RESET_VAL(32'h0)
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) mcause_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mcause_d),
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.we_i(mcause_we),
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.rdata_o(mcause_q)
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);
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// mepc
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csr #(
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.RESET_VAL(32'h0)
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) mepc_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mepc_d),
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.we_i(mepc_we),
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.rdata_o(mepc_q)
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);
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// mie
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csr #(
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.RESET_VAL(32'h0)
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) mie_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mie_d),
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.we_i(mie_we),
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.rdata_o(mie_q)
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);
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// mstatus
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csr #(
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.RESET_VAL(32'h0)
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) mstatus_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mstatus_d),
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.we_i(mstatus_we),
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.rdata_o(mstatus_q)
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);
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// mscratch
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csr #(
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.RESET_VAL(32'h0)
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) mscratch_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mscratch_d),
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.we_i(mscratch_we),
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.rdata_o(mscratch_q)
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);
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// dscratch0
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csr #(
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.RESET_VAL(32'h0)
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) dscratch0_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dscratch0_d),
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.we_i(dscratch0_we),
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.rdata_o(dscratch0_q)
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);
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// dscratch1
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csr #(
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.RESET_VAL(32'h0)
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) dscratch1_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dscratch1_d),
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.we_i(dscratch1_we),
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.rdata_o(dscratch1_q)
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);
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// mhartid
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csr #(
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.RESET_VAL(32'h0)
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) mhartid_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mhartid_d),
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.we_i(mhartid_we),
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.rdata_o(mhartid_q)
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);
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// dpc
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csr #(
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.RESET_VAL(32'h0)
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) dpc_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dpc_d),
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.we_i(dpc_we),
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.rdata_o(dpc_q)
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);
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// dcsr
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csr #(
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.RESET_VAL(32'h0)
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) dcsr_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dcsr_d),
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.we_i(dcsr_we),
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.rdata_o(dcsr_q)
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);
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endmodule
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