tinyriscv/rtl
liangkangnan d6a14415c9 rtl: optimized for instr fetch and mem access
Signed-off-by: liangkangnan <liangkangnan@163.com>
2023-03-28 10:19:07 +08:00
..
core rtl: optimized for instr fetch and mem access 2023-03-28 10:19:07 +08:00
debug rtl: optimized for instr fetch and mem access 2023-03-28 10:19:07 +08:00
perips rtl:perips:flash_ctrl: fix read state 2021-11-16 15:24:37 +08:00
sys_bus rtl:sys_bus: fix only select one master 2023-03-21 17:54:36 +08:00
utils rtl:utils: add async_fifo module 2023-03-23 20:47:51 +08:00