77 lines
2.5 KiB
Verilog
77 lines
2.5 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// common reg module
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module regs (
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input wire clk,
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input wire rst,
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input wire we, // reg write enable
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input wire[`RegAddrBus] waddr, // reg write addr
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input wire[`RegBus] wdata, // reg write data
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input wire re1, // reg1 read enable
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input wire[`RegAddrBus] raddr1, // reg1 read addr
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output reg[`RegBus] rdata1, // reg1 read data
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input wire re2, // reg2 read enable
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input wire[`RegAddrBus] raddr2, // reg2 read addr
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output reg[`RegBus] rdata2 // reg2 read data
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);
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reg[`RegBus] regs[0:`RegNum - 1];
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// write reg
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always @ (posedge clk) begin
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if (rst == `RstDisable) begin
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if((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin
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regs[waddr] <= wdata;
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end
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end
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end
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// read reg1
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always @ (*) begin
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if(rst == `RstEnable) begin
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rdata1 <= `ZeroWord;
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end else if(raddr1 == `RegNumLog2'h0) begin
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rdata1 <= `ZeroWord;
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end else if(re1 == `ReadEnable) begin
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rdata1 <= regs[raddr1];
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end else begin
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rdata1 <= `ZeroWord;
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end
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end
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// read reg2
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always @ (*) begin
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if(rst == `RstEnable) begin
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rdata2 <= `ZeroWord;
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end else if(raddr2 == `RegNumLog2'h0) begin
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rdata2 <= `ZeroWord;
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end else if(re2 == `ReadEnable) begin
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rdata2 <= regs[raddr2];
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end else begin
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rdata2 <= `ZeroWord;
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end
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end
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endmodule
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