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tinyriscv/sim
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liangkangnan ae3ff5a211 rtl🚌 use gnt and rvalid signal 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 		2021-09-01 09:54:32 +08:00
..
remote_bitbang tmp commit, unstable 2021-03-29 15:14:50 +08:00
.gitignore tmp commit, unstable 2021-03-29 15:14:50 +08:00
Makefile debug: add hw breakpoint support 2021-05-14 14:37:47 +08:00
README.md tmp commit, unstable 2021-03-29 15:14:50 +08:00
jtag_compliance_test.cfg temp commit 2021-05-11 10:35:36 +08:00
jtag_debug.cfg debug: add hw breakpoint support 2021-05-14 14:37:47 +08:00
sim_ctrl.sv rtl🚌 use gnt and rvalid signal 2021-09-01 09:54:32 +08:00
sim_jtag.sv tmp commit, unstable 2021-03-29 15:14:50 +08:00
tb_top_verilator.cpp sim: add dump wave enable by softwave 2021-08-20 11:50:21 +08:00
tb_top_verilator.sv sim: add dump wave enable by softwave 2021-08-20 11:50:21 +08:00

README.md