tinyriscv

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liangkangnan 05e2441d24 temp commit Signed-off-by: liangkangnan <liangkangnan@163.com>		2021-04-13 16:34:00 +08:00
doc	first release	2020-10-23 21:26:18 +08:00
fpga	rtl: add reset ctrl module	2020-11-18 22:15:08 +08:00
pic	pic: update arch.jpg	2020-06-27 10:11:46 +08:00
rtl	temp commit	2021-04-13 16:34:00 +08:00
sdk	temp commit	2021-04-13 11:10:06 +08:00
sim	rtl: add reset module	2021-04-13 14:12:47 +08:00
tests	test:example: move C examples to sdk directory	2020-11-08 22:09:38 +08:00
tools	tools: add openocd ex arrt	2021-03-29 19:21:02 +08:00
.gitignore	first release	2020-10-23 21:26:18 +08:00
LICENSE	…
README.md	temp commit	2021-03-31 15:25:22 +08:00
rtl.flist	rtl: add reset module	2021-04-13 14:12:47 +08:00

更新计划： 1.增加指令trace功能； 2.总线优化； 3.取指、访存优化； 4.jtag优化；