57 lines
1.8 KiB
Verilog
57 lines
1.8 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// ram module
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module ram(
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input wire clk,
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input wire rst,
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input wire we_i, // write enable
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input wire[`MemAddrBus] addr_i, // addr
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input wire[`MemBus] data_i,
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input wire req_i,
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output reg[`MemBus] data_o, // read data
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output reg ack_o
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);
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reg[`MemBus] _ram[0:`MemNum - 1];
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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ack_o <= `RIB_ACK;
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end else begin
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if (we_i == `WriteEnable) begin
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_ram[addr_i[31:2]] <= data_i;
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end
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end
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end
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always @ (*) begin
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if (rst == `RstEnable) begin
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data_o <= `ZeroWord;
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end else begin
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data_o <= _ram[addr_i[31:2]];
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end
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end
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endmodule
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