tinyriscv/rtl/core
liangkangnan 43aca8195c add clint hold input signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-04-25 17:08:46 +08:00
..
clint.v support preemption 2020-04-25 17:03:13 +08:00
csr_reg.v add code comments 2020-04-18 20:14:37 +08:00
ctrl.v add clint hold input signal 2020-04-25 17:08:46 +08:00
defines.v add mepc reg 2020-04-18 11:22:20 +08:00
div.v stop div when interrupt assert 2020-04-25 17:04:44 +08:00
ex.v stop div when interrupt assert 2020-04-25 17:04:44 +08:00
id.v add code comments 2020-04-18 20:14:37 +08:00
id_ex.v add code comments 2020-04-18 20:14:37 +08:00
if_id.v add code comments 2020-04-18 20:14:37 +08:00
pc_reg.v add code comments 2020-04-18 20:14:37 +08:00
regs.v add code comments 2020-04-18 20:14:37 +08:00
rib.v add code comments 2020-04-18 20:14:37 +08:00
tinyriscv.v add code comments 2020-04-18 20:14:37 +08:00