tinyriscv/rtl/debug
liangkangnan b3cfa2dfa6 rtl: do not need request all the access period
Signed-off-by: liangkangnan <liangkangnan@163.com>
2023-04-01 14:12:59 +08:00
..
debug_rom.sv temp commit 2021-05-04 21:11:43 +08:00
jtag_def.sv debug: change dmi addr bits to 7 2021-05-28 10:37:50 +08:00
jtag_dm.sv rtl: optimized for instr fetch and mem access 2023-03-28 10:19:07 +08:00
jtag_dmi.sv debug: change dmi addr bits to 7 2021-05-28 10:37:50 +08:00
jtag_dtm.sv rtl: optimized for instr fetch and mem access 2023-03-28 10:19:07 +08:00
jtag_mem.sv rtl🚌 use gnt and rvalid signal 2021-09-01 09:54:32 +08:00
jtag_sba.sv rtl: do not need request all the access period 2023-04-01 14:12:59 +08:00
jtag_tap.sv temp commit 2021-05-31 10:27:01 +08:00
jtag_top.sv rtl🚌 use gnt and rvalid signal 2021-09-01 09:54:32 +08:00