215 lines
6.9 KiB
Systemverilog
215 lines
6.9 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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module exu_mem(
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input wire clk,
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input wire rst_n,
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input req_mem_i,
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input wire[31:0] mem_addr_i,
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input wire[31:0] mem_rs2_data_i,
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input wire[31:0] mem_rdata_i,
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input wire mem_gnt_i,
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input wire mem_rvalid_i,
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input wire mem_op_lb_i,
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input wire mem_op_lh_i,
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input wire mem_op_lw_i,
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input wire mem_op_lbu_i,
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input wire mem_op_lhu_i,
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input wire mem_op_sb_i,
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input wire mem_op_sh_i,
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input wire mem_op_sw_i,
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output wire mem_access_misaligned_o,
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output wire mem_stall_o,
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output wire[31:0] mem_addr_o,
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output wire[31:0] mem_wdata_o,
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output wire mem_reg_we_o,
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output wire mem_mem_we_o,
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output wire[3:0] mem_be_o,
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output wire mem_req_o
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);
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wire[1:0] mem_addr_index = mem_addr_i[1:0];
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wire mem_addr_index00 = (mem_addr_index == 2'b00);
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wire mem_addr_index01 = (mem_addr_index == 2'b01);
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wire mem_addr_index10 = (mem_addr_index == 2'b10);
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wire mem_addr_index11 = (mem_addr_index == 2'b11);
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assign mem_be_o[0] = mem_addr_index00 | mem_op_sw_i;
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assign mem_be_o[1] = mem_addr_index01 | (mem_op_sh_i & mem_addr_index00) | mem_op_sw_i;
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assign mem_be_o[2] = mem_addr_index10 | mem_op_sw_i;
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assign mem_be_o[3] = mem_addr_index11 | (mem_op_sh_i & mem_addr_index10) | mem_op_sw_i;
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reg[31:0] sb_res;
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always @ (*) begin
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sb_res = 32'h0;
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case (1'b1)
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mem_addr_index00: sb_res = {24'h0, mem_rs2_data_i[7:0]};
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mem_addr_index01: sb_res = {16'h0, mem_rs2_data_i[7:0], 8'h0};
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mem_addr_index10: sb_res = {8'h0, mem_rs2_data_i[7:0], 16'h0};
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mem_addr_index11: sb_res = {mem_rs2_data_i[7:0], 24'h0};
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endcase
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end
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reg[31:0] sh_res;
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always @ (*) begin
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sh_res = 32'h0;
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case (1'b1)
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mem_addr_index00: sh_res = {16'h0, mem_rs2_data_i[15:0]};
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mem_addr_index10: sh_res = {mem_rs2_data_i[15:0], 16'h0};
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endcase
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end
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wire[31:0] sw_res = mem_rs2_data_i;
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reg[31:0] lb_res;
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always @ (*) begin
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lb_res = 32'h0;
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case (1'b1)
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mem_addr_index00: lb_res = {{24{mem_op_lb_i & mem_rdata_i[7]}}, mem_rdata_i[7:0]};
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mem_addr_index01: lb_res = {{24{mem_op_lb_i & mem_rdata_i[15]}}, mem_rdata_i[15:8]};
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mem_addr_index10: lb_res = {{24{mem_op_lb_i & mem_rdata_i[23]}}, mem_rdata_i[23:16]};
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mem_addr_index11: lb_res = {{24{mem_op_lb_i & mem_rdata_i[31]}}, mem_rdata_i[31:24]};
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endcase
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end
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reg[31:0] lh_res;
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always @ (*) begin
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lh_res = 32'h0;
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case (1'b1)
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mem_addr_index00: lh_res = {{24{mem_op_lh_i & mem_rdata_i[15]}}, mem_rdata_i[15:0]};
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mem_addr_index10: lh_res = {{24{mem_op_lh_i & mem_rdata_i[31]}}, mem_rdata_i[31:16]};
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endcase
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end
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wire[31:0] lw_res = mem_rdata_i;
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reg[31:0] mem_wdata;
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always @ (*) begin
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mem_wdata = 32'h0;
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case (1'b1)
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mem_op_sb_i: mem_wdata = sb_res;
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mem_op_sh_i: mem_wdata = sh_res;
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mem_op_sw_i: mem_wdata = sw_res;
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mem_op_lb_i: mem_wdata = lb_res;
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mem_op_lbu_i: mem_wdata = lb_res;
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mem_op_lh_i: mem_wdata = lh_res;
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mem_op_lhu_i: mem_wdata = lh_res;
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mem_op_lw_i: mem_wdata = lw_res;
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endcase
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end
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assign mem_wdata_o = mem_wdata;
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wire op_load = mem_op_lb_i | mem_op_lh_i | mem_op_lw_i | mem_op_lbu_i | mem_op_lhu_i;
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wire op_store = mem_op_sb_i | mem_op_sh_i | mem_op_sw_i;
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localparam S_IDLE = 3'b001;
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localparam S_WAIT_READ = 3'b010;
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localparam S_WAIT_WRITE = 3'b100;
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reg[2:0] state_d, state_q;
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reg mem_stall_d;
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reg mem_reg_we_d;
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reg mem_mem_we_d;
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reg req_mem_d;
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// 访存状态机
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always @ (*) begin
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state_d = state_q;
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mem_stall_d = 1'b0;
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mem_reg_we_d = 1'b0;
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mem_mem_we_d = 1'b0;
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req_mem_d = 1'b0;
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case (state_q)
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S_IDLE: begin
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if (req_mem_i) begin
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mem_stall_d = 1'b1;
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req_mem_d = 1'b1;
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if (mem_gnt_i) begin
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if (op_load) begin
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state_d = S_WAIT_READ;
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end else if (op_store) begin
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state_d = S_WAIT_WRITE;
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mem_mem_we_d = 1'b1;
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end
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end
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end
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end
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// 读内存
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S_WAIT_READ: begin
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mem_stall_d = 1'b1;
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if (mem_rvalid_i) begin
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state_d = S_IDLE;
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mem_reg_we_d = 1'b1;
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mem_stall_d = 1'b0;
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end
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end
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// 写内存
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S_WAIT_WRITE: begin
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mem_stall_d = 1'b1;
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if (mem_rvalid_i) begin
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state_d = S_IDLE;
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mem_stall_d = 1'b0;
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end
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end
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default: ;
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endcase
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end
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// 访存请求
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assign mem_req_o = req_mem_d;
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// 访存地址
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assign mem_addr_o = mem_addr_i;
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// 暂停流水线
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assign mem_stall_o = mem_stall_d;
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// 写寄存器使能
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assign mem_reg_we_o = mem_reg_we_d;
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// 写内存使能
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assign mem_mem_we_o = mem_mem_we_d;
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assign mem_access_misaligned_o = (mem_op_sw_i | mem_op_lw_i)? (mem_addr_i[0] | mem_addr_i[1]):
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(mem_op_sh_i | mem_op_lh_i | mem_op_lhu_i)? mem_addr_i[0]:
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0;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_q <= S_IDLE;
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end else begin
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state_q <= state_d;
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end
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end
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endmodule
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