bin.tcl
|
fpga: xilinx: cmod_a7: add bin.tcl and mcs.tcl
|
2022-08-12 19:33:49 +08:00 |
bit.tcl
|
fpga: xilinx: cmod_a7: add bin.tcl and mcs.tcl
|
2022-08-12 19:33:49 +08:00 |
impl.tcl
|
rtl: move top module into fpga dir
|
2022-08-10 08:13:38 +08:00 |
init.tcl
|
fpga: xilinx: cmod_a7: add bin.tcl and mcs.tcl
|
2022-08-12 19:33:49 +08:00 |
mcs.tcl
|
fpga: xilinx: cmod_a7: add bin.tcl and mcs.tcl
|
2022-08-12 19:33:49 +08:00 |
report.tcl
|
rtl: move top module into fpga dir
|
2022-08-10 08:13:38 +08:00 |
synth.tcl
|
rtl: move top module into fpga dir
|
2022-08-10 08:13:38 +08:00 |