tinyriscv/tests/isa/generated/rv32ui-p-fence_i.verilog

29 lines
1.2 KiB
Plaintext

@00000000
13 0D 00 00 93 0D 00 00 93 06 F0 06 17 15 00 00
03 15 45 FF 97 15 00 00 83 95 E5 FE 13 00 00 00
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
97 02 00 00 23 9A A2 00 97 02 00 00 23 97 B2 00
0F 10 00 00 93 86 E6 0D 13 00 00 00 93 0E C0 1B
93 01 20 00 63 9A D6 07 13 07 40 06 13 07 F7 FF
E3 1E 07 FE 97 02 00 00 23 96 A2 04 97 02 00 00
23 93 B2 04 0F 10 00 00 13 00 00 00 13 00 00 00
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
93 86 B6 22 13 00 00 00 93 0E 90 30 93 01 30 00
63 94 D6 01 63 18 30 00 13 0D 10 00 93 0D 00 00
6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
@00001000
93 86 D6 14 00 00 00 00 00 00 00 00 00 00 00 00
@00001040
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00