150 lines
3.2 KiB
Verilog
150 lines
3.2 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 带默认值和控制信号的流水线触发器
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module gen_pipe_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire hold_en,
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input wire[DW-1:0] def_val,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
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always @ (posedge clk) begin
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if (!rst | hold_en) begin
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qout_r <= def_val;
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end else begin
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qout_r <= din;
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end
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end
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assign qout = qout_r;
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endmodule
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// 复位后输出为0的触发器
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module gen_rst_0_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
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always @ (posedge clk) begin
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if (!rst) begin
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qout_r <= {DW{1'b0}};
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end else begin
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qout_r <= din;
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end
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end
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assign qout = qout_r;
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endmodule
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// 复位后输出为1的触发器
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module gen_rst_1_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
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always @ (posedge clk) begin
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if (!rst) begin
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qout_r <= {DW{1'b1}};
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end else begin
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qout_r <= din;
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end
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end
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assign qout = qout_r;
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endmodule
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// 复位后输出为默认值的触发器
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module gen_rst_def_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire[DW-1:0] def_val,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
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always @ (posedge clk) begin
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if (!rst) begin
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qout_r <= def_val;
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end else begin
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qout_r <= din;
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end
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end
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assign qout = qout_r;
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endmodule
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// 带使能端、复位后输出为0的触发器
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module gen_en_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire en,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
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always @ (posedge clk) begin
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if (!rst) begin
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qout_r <= {DW{1'b0}};
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end else if (en == 1'b1) begin
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qout_r <= din;
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end
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end
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assign qout = qout_r;
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endmodule
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