53 lines
2.0 KiB
Verilog
53 lines
2.0 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// 将指令向译码模块传递
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module if_id(
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input wire clk,
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input wire rst,
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input wire[`InstBus] inst_i, // 指令内容
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input wire[`InstAddrBus] inst_addr_i, // 指令地址
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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input wire[`INT_BUS] int_flag_i, // 外设中断输入信号
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output wire[`INT_BUS] int_flag_o,
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output wire[`InstBus] inst_o, // 指令内容
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output wire[`InstAddrBus] inst_addr_o // 指令地址
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);
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wire hold_en = (hold_flag_i >= `Hold_If);
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wire[`InstBus] inst;
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gen_pipe_dff #(32) inst_ff(clk, rst, hold_en, `INST_NOP, inst_i, inst);
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assign inst_o = inst;
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wire[`InstAddrBus] inst_addr;
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gen_pipe_dff #(32) inst_addr_ff(clk, rst, hold_en, `ZeroWord, inst_addr_i, inst_addr);
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assign inst_addr_o = inst_addr;
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wire[`INT_BUS] int_flag;
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gen_pipe_dff #(8) int_ff(clk, rst, hold_en, `INT_NONE, int_flag_i, int_flag);
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assign int_flag_o = int_flag;
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endmodule
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