73 lines
2.8 KiB
Python
73 lines
2.8 KiB
Python
import sys
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import filecmp
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import subprocess
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import sys
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import os
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# 主函数
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def main():
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rtl_dir = '..'
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tb_file = r'/tb/jtag_tb.v'
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# iverilog程序
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iverilog_cmd = ['iverilog']
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# 顶层模块
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#iverilog_cmd += ['-s', r'tinyriscv_soc_tb']
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# 编译生成文件
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iverilog_cmd += ['-o', r'out.vvp']
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# 头文件(defines.v)路径
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iverilog_cmd += ['-I', rtl_dir + r'/rtl/core']
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# 宏定义，仿真输出文件
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iverilog_cmd += ['-D', r'OUTPUT="signature.output"']
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# testbench文件
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iverilog_cmd.append(rtl_dir + tb_file)
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# ../rtl/core
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iverilog_cmd.append(rtl_dir + r'/rtl/core/clint.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/csr_reg.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/defines.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/divider.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/exu.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/exu_alu_datapath.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/exu_commit.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/exu_dispatch.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/exu_mem.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/exu_muldiv.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/gpr_reg.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/idu.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/idu_exu.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/ifu.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/ifu_idu.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/pipe_ctrl.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/tinyriscv_core.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/core/rst_ctrl.v')
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# ../rtl/perips
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iverilog_cmd.append(rtl_dir + r'/rtl/perips/ram.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/perips/rom.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/perips/timer.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/perips/uart.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/perips/gpio.v')
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# ../rtl/debug
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iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_dm.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_driver.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_top.v')
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# ../rtl/sys_bus
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iverilog_cmd.append(rtl_dir + r'/rtl/sys_bus/rib.v')
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# ../rtl/utils
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iverilog_cmd.append(rtl_dir + r'/rtl/utils/full_handshake_rx.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/utils/full_handshake_tx.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/utils/gen_buf.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/utils/gen_dff.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/utils/gen_ram.v')
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iverilog_cmd.append(rtl_dir + r'/rtl/utils/vld_rdy.v')
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# ../rtl/top
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iverilog_cmd.append(rtl_dir + r'/rtl/top/tinyriscv_soc_top.v')
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# 编译
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process = subprocess.Popen(iverilog_cmd)
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process.wait(timeout=5)
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if __name__ == '__main__':
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sys.exit(main())
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