73 lines
2.2 KiB
Verilog
73 lines
2.2 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.v"
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module gen_ram #(
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parameter DP = 512,
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parameter DW = 32,
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parameter MW = 4,
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parameter AW = 32)(
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input wire clk,
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input wire[AW-1:0] addr_i,
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input wire[DW-1:0] data_i,
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input wire[MW-1:0] sel_i,
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input wire we_i,
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output wire[DW-1:0] data_o
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);
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reg[DW-1:0] ram [0:DP-1];
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reg[AW-1:0] addr_r;
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wire[MW-1:0] wen;
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wire ren;
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assign ren = (~we_i);
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assign wen = ({MW{we_i}} & sel_i);
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always @ (posedge clk) begin
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if (ren) begin
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addr_r <= addr_i;
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end
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end
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assign data_o = ram[addr_r];
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genvar i;
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generate
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for (i = 0; i < MW; i = i + 1) begin: sel_width
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if ((8 * i + 8) > DW) begin: i_gt_8
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always @ (posedge clk) begin: i_gt_8_ff
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if (wen[i]) begin: gt_8_wen
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ram[addr_i][DW-1:8*i] <= data_i[DW-1:8*i];
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end
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end
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end else begin: i_lt_8
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always @ (posedge clk) begin: i_lt_8_ff
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if (wen[i]) begin: lt_8_wen
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ram[addr_i][8*i+7:8*i] <= data_i[8*i+7:8*i];
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end
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end
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end
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end
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endgenerate
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endmodule
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