// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`


module rvic_reg_top (
  input  logic        clk_i,
  input  logic        rst_ni,

  // To HW
  output rvic_reg_pkg::rvic_reg2hw_t reg2hw, // Write
  input  rvic_reg_pkg::rvic_hw2reg_t hw2reg, // Read

  input  logic        reg_we,
  input  logic        reg_re,
  input  logic [31:0] reg_wdata,
  input  logic [ 3:0] reg_be,
  input  logic [31:0] reg_addr,
  output logic [31:0] reg_rdata
);

  import rvic_reg_pkg::* ;

  localparam int AW = 6;
  localparam int DW = 32;
  localparam int DBW = DW/8;    // Byte Width

  logic reg_error;
  logic addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;

  assign reg_rdata = reg_rdata_next;
  assign reg_error = wr_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic enable_we;
  logic [31:0] enable_qs;
  logic [31:0] enable_wd;
  logic pending_we;
  logic [31:0] pending_qs;
  logic [31:0] pending_wd;
  logic priority0_we;
  logic [31:0] priority0_qs;
  logic [31:0] priority0_wd;
  logic priority1_we;
  logic [31:0] priority1_qs;
  logic [31:0] priority1_wd;
  logic priority2_we;
  logic [31:0] priority2_qs;
  logic [31:0] priority2_wd;
  logic priority3_we;
  logic [31:0] priority3_qs;
  logic [31:0] priority3_wd;
  logic priority4_we;
  logic [31:0] priority4_qs;
  logic [31:0] priority4_wd;
  logic priority5_we;
  logic [31:0] priority5_qs;
  logic [31:0] priority5_wd;
  logic priority6_we;
  logic [31:0] priority6_qs;
  logic [31:0] priority6_wd;
  logic priority7_we;
  logic [31:0] priority7_qs;
  logic [31:0] priority7_wd;

  // Register instances
  // R[enable]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_enable (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (enable_we),
    .wd     (enable_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.enable.q),

    // to register interface (read)
    .qs     (enable_qs)
  );


  // R[pending]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("W1C"),
    .RESVAL  (32'h0)
  ) u_pending (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (pending_we),
    .wd     (pending_wd),

    // from internal hardware
    .de     (hw2reg.pending.de),
    .d      (hw2reg.pending.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.pending.q),

    // to register interface (read)
    .qs     (pending_qs)
  );


  // R[priority0]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority0_we),
    .wd     (priority0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority0.q),

    // to register interface (read)
    .qs     (priority0_qs)
  );


  // R[priority1]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority1_we),
    .wd     (priority1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority1.q),

    // to register interface (read)
    .qs     (priority1_qs)
  );


  // R[priority2]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority2_we),
    .wd     (priority2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority2.q),

    // to register interface (read)
    .qs     (priority2_qs)
  );


  // R[priority3]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority3_we),
    .wd     (priority3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority3.q),

    // to register interface (read)
    .qs     (priority3_qs)
  );


  // R[priority4]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority4_we),
    .wd     (priority4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority4.q),

    // to register interface (read)
    .qs     (priority4_qs)
  );


  // R[priority5]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority5_we),
    .wd     (priority5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority5.q),

    // to register interface (read)
    .qs     (priority5_qs)
  );


  // R[priority6]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority6_we),
    .wd     (priority6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority6.q),

    // to register interface (read)
    .qs     (priority6_qs)
  );


  // R[priority7]: V(False)

  prim_subreg #(
    .DW      (32),
    .SWACCESS("RW"),
    .RESVAL  (32'h0)
  ) u_priority7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (priority7_we),
    .wd     (priority7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.priority7.q),

    // to register interface (read)
    .qs     (priority7_qs)
  );


  logic [9:0] addr_hit;
  always_comb begin
    addr_hit = '0;
    addr_hit[0] = (reg_addr == RVIC_ENABLE_OFFSET);
    addr_hit[1] = (reg_addr == RVIC_PENDING_OFFSET);
    addr_hit[2] = (reg_addr == RVIC_PRIORITY0_OFFSET);
    addr_hit[3] = (reg_addr == RVIC_PRIORITY1_OFFSET);
    addr_hit[4] = (reg_addr == RVIC_PRIORITY2_OFFSET);
    addr_hit[5] = (reg_addr == RVIC_PRIORITY3_OFFSET);
    addr_hit[6] = (reg_addr == RVIC_PRIORITY4_OFFSET);
    addr_hit[7] = (reg_addr == RVIC_PRIORITY5_OFFSET);
    addr_hit[8] = (reg_addr == RVIC_PRIORITY6_OFFSET);
    addr_hit[9] = (reg_addr == RVIC_PRIORITY7_OFFSET);
  end

  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;

  // Check sub-word write is permitted
  always_comb begin
    wr_err = (reg_we &
              ((addr_hit[0] & (|(RVIC_PERMIT[0] & ~reg_be))) |
               (addr_hit[1] & (|(RVIC_PERMIT[1] & ~reg_be))) |
               (addr_hit[2] & (|(RVIC_PERMIT[2] & ~reg_be))) |
               (addr_hit[3] & (|(RVIC_PERMIT[3] & ~reg_be))) |
               (addr_hit[4] & (|(RVIC_PERMIT[4] & ~reg_be))) |
               (addr_hit[5] & (|(RVIC_PERMIT[5] & ~reg_be))) |
               (addr_hit[6] & (|(RVIC_PERMIT[6] & ~reg_be))) |
               (addr_hit[7] & (|(RVIC_PERMIT[7] & ~reg_be))) |
               (addr_hit[8] & (|(RVIC_PERMIT[8] & ~reg_be))) |
               (addr_hit[9] & (|(RVIC_PERMIT[9] & ~reg_be)))));
  end

  assign enable_we = addr_hit[0] & reg_we & !reg_error;

  assign enable_wd = reg_wdata[31:0];
  assign pending_we = addr_hit[1] & reg_we & !reg_error;

  assign pending_wd = reg_wdata[31:0];
  assign priority0_we = addr_hit[2] & reg_we & !reg_error;

  assign priority0_wd = reg_wdata[31:0];
  assign priority1_we = addr_hit[3] & reg_we & !reg_error;

  assign priority1_wd = reg_wdata[31:0];
  assign priority2_we = addr_hit[4] & reg_we & !reg_error;

  assign priority2_wd = reg_wdata[31:0];
  assign priority3_we = addr_hit[5] & reg_we & !reg_error;

  assign priority3_wd = reg_wdata[31:0];
  assign priority4_we = addr_hit[6] & reg_we & !reg_error;

  assign priority4_wd = reg_wdata[31:0];
  assign priority5_we = addr_hit[7] & reg_we & !reg_error;

  assign priority5_wd = reg_wdata[31:0];
  assign priority6_we = addr_hit[8] & reg_we & !reg_error;

  assign priority6_wd = reg_wdata[31:0];
  assign priority7_we = addr_hit[9] & reg_we & !reg_error;

  assign priority7_wd = reg_wdata[31:0];

  // Read data return
  always_comb begin
    reg_rdata_next = '0;
    unique case (1'b1)
      addr_hit[0]: begin
        reg_rdata_next[31:0] = enable_qs;
      end

      addr_hit[1]: begin
        reg_rdata_next[31:0] = pending_qs;
      end

      addr_hit[2]: begin
        reg_rdata_next[31:0] = priority0_qs;
      end

      addr_hit[3]: begin
        reg_rdata_next[31:0] = priority1_qs;
      end

      addr_hit[4]: begin
        reg_rdata_next[31:0] = priority2_qs;
      end

      addr_hit[5]: begin
        reg_rdata_next[31:0] = priority3_qs;
      end

      addr_hit[6]: begin
        reg_rdata_next[31:0] = priority4_qs;
      end

      addr_hit[7]: begin
        reg_rdata_next[31:0] = priority5_qs;
      end

      addr_hit[8]: begin
        reg_rdata_next[31:0] = priority6_qs;
      end

      addr_hit[9]: begin
        reg_rdata_next[31:0] = priority7_qs;
      end

      default: begin
        reg_rdata_next = '1;
      end
    endcase
  end

  // Unused signal tieoff

  // wdata / byte enable are not always fully used
  // add a blanket unused statement to handle lint waivers
  logic unused_wdata;
  logic unused_be;
  assign unused_wdata = ^reg_wdata;
  assign unused_be = ^reg_be;

endmodule