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Commit Graph

  • 043bc23f8a use = instead of <= in combination logic liangkangnan 2020-05-02 11:57:25 +0800
  • d7bdc35911 fix uninitial reg var liangkangnan 2020-05-02 11:53:48 +0800
  • 9edcc08634 add FPGA port liangkangnan 2020-05-01 17:07:02 +0800
  • 6a197d4a45 add weiyun download liangkangnan 2020-04-29 21:47:39 +0800
  • 4505067a95 add doc liangkangnan 2020-04-29 21:16:36 +0800
  • c38d288657 update liangkangnan 2020-04-25 20:19:03 +0800
  • ea21ca6a38 FPGA: add README.md liangkangnan 2020-04-25 20:13:58 +0800
  • c40dd0c603 update v2.2 liangkangnan 2020-04-25 17:34:58 +0800
  • 39750cffc8 add freertos liangkangnan 2020-04-25 17:24:51 +0800
  • aead35700c add signal liangkangnan 2020-04-25 17:15:46 +0800
  • d92352e1c2 use relative include path liangkangnan 2020-04-25 17:15:00 +0800
  • 02d19b9e6f add mie and mstatus reg liangkangnan 2020-04-25 17:13:12 +0800
  • 4a530ab894 add ECALL inst liangkangnan 2020-04-25 17:11:53 +0800
  • 02bcee9aa9 sync for different clock liangkangnan 2020-04-25 17:10:11 +0800
  • 43aca8195c add clint hold input signal liangkangnan 2020-04-25 17:08:46 +0800
  • db8a65ebf4 use larger rom and ram for more example liangkangnan 2020-04-25 17:07:31 +0800
  • f110a2c0e0 set MPIE and MPP liangkangnan 2020-04-25 17:05:48 +0800
  • 6cf86e0286 stop div when interrupt assert liangkangnan 2020-04-25 17:04:44 +0800
  • 09513f8f2c support preemption liangkangnan 2020-04-25 17:03:13 +0800
  • 0ac39d9cdd add FPGA xdc file liangkangnan 2020-04-25 16:59:23 +0800
  • 7434cad275 example: add FreeRTOS liangkangnan 2020-04-25 16:57:57 +0800
  • 39af40a476 add FPGA clock liangkangnan 2020-04-19 11:05:08 +0800
  • 69321f870e add other liangkangnan 2020-04-19 10:55:53 +0800
  • f1f89f7bf5 add toolchain and mcmodel configuration liangkangnan 2020-04-18 21:27:26 +0800
  • ea9b4de53d update liangkangnan 2020-04-18 20:53:34 +0800
  • 7708930ecf update liangkangnan 2020-04-18 20:49:42 +0800
  • 57ca3832a0 add C example instruction liangkangnan 2020-04-18 20:42:20 +0800
  • dcac95dfab add code comments liangkangnan 2020-04-18 20:14:37 +0800
  • 73098bdcd8 optimized liangkangnan 2020-04-18 11:39:27 +0800
  • 18577d9b61 use oneshot mode liangkangnan 2020-04-18 11:37:22 +0800
  • ce225394df fix reg1 reg2 bits width liangkangnan 2020-04-18 11:35:43 +0800
  • b29781a8de optimize div liangkangnan 2020-04-18 11:23:46 +0800
  • 2638240d0b add mepc reg liangkangnan 2020-04-18 11:22:20 +0800
  • 96f8d6e5a0 optimized: use statemachine liangkangnan 2020-04-18 11:21:09 +0800
  • 59acc36185 update coremark liangkangnan 2020-04-12 19:51:03 +0800
  • ef8f1d5ca9 uart_tx: update liangkangnan 2020-04-12 19:38:26 +0800
  • ba91618324 add uart.c liangkangnan 2020-04-12 19:36:06 +0800
  • 356e47b543 update liangkangnan 2020-04-12 17:58:13 +0800
  • 39fb6311da add coremark v2.1 liangkangnan 2020-04-12 15:21:26 +0800
  • 3771cba0aa add coremark score liangkangnan 2020-04-11 22:43:23 +0800
  • 0c79eef623 example: add coremark liangkangnan 2020-04-11 22:30:09 +0800
  • cf7862f50c add README.md liangkangnan 2020-04-11 19:40:36 +0800
  • 0e188d4934 reorganize example and optimize interrupt liangkangnan 2020-04-11 19:03:49 +0800
  • 20d1055ea4 example: reorganization liangkangnan 2020-04-06 21:28:56 +0800
  • 115a8ea384 pic: add addr_alloc.jpg liangkangnan 2020-04-06 20:29:57 +0800
  • 36a2ffdf5a example: add uart_tx liangkangnan 2020-04-06 20:20:31 +0800
  • b2827b2fb4 uart: update liangkangnan 2020-04-06 19:54:40 +0800
  • 000bb19ad2 example: add gpio liangkangnan 2020-04-06 17:19:53 +0800
  • e714a0ba63 add write dpc liangkangnan 2020-04-06 14:34:12 +0800
  • c934727ea8 update liangkangnan 2020-04-05 22:45:53 +0800
  • 66967e9bb0 pic: update arch.jpg liangkangnan 2020-04-05 22:35:35 +0800
  • a68f31b604 perips: add uart_tx and gpio liangkangnan 2020-04-05 22:27:00 +0800
  • 6660f18b3d support CSR inst liangkangnan 2020-04-05 22:22:34 +0800
  • ecb9fca8c1 update v2.0 liangkangnan 2020-03-29 23:19:14 +0800
  • 7d9dc3f83a update liangkangnan 2020-03-21 18:02:40 +0800
  • c57f3cf121 update liangkangnan 2020-03-21 13:58:24 +0800
  • a224aa1d59 update liangkangnan 2020-03-08 15:35:07 +0800
  • a4148afa4d update liangkangnan 2020-03-08 15:29:53 +0800
  • 150ca7ca2b update liangkangnan 2020-03-08 15:14:04 +0800
  • 8b51737477 add interrupt support and example v1.1 liangkangnan 2020-03-08 15:09:30 +0800
  • c7c9193982 add peripheral: timer liangkangnan 2020-03-08 15:07:17 +0800
  • 429f5de88a update v1.0 liangkangnan 2020-03-03 20:47:55 +0800
  • 534dba1706 update liangkangnan 2020-03-01 17:20:05 +0800
  • 97afab88d6 add openocd liangkangnan 2020-03-01 15:17:39 +0800
  • 6fe9278908 update liangkangnan 2020-03-01 15:16:39 +0800
  • 8208cbc100 support JTAG liangkangnan 2020-03-01 14:55:36 +0800
  • 02f61aff40 update liangkangnan 2020-02-23 19:57:35 +0800
  • 0d4e8bb5f4 improve ex module liangkangnan 2020-02-23 17:51:55 +0800
  • 076610fb0d rename openriscv to tinyriscv liangkangnan 2020-02-23 17:01:45 +0800
  • 97c7cee0ad return to IDLE state when div completed liangkangnan 2020-02-22 20:38:16 +0800
  • 3b1807c467 fix: multi drive error liangkangnan 2020-02-22 15:24:10 +0800
  • f0bd0845d6 fix implementation error by EDA tool liangkangnan 2020-02-16 21:27:11 +0800
  • 81391089ea update README.md Blue Liang 2020-01-13 08:51:13 +0800
  • 2b174b2518 update README.md Blue Liang 2020-01-13 08:45:24 +0800
  • 9420b85796 add div inst Blue Liang 2020-01-13 08:26:41 +0800
  • af74c11db8 descrption: add mul instruction Blue Liang 2020-01-02 17:14:45 +0800
  • 97efd66e78 add mul instruction Blue Liang 2020-01-02 16:12:13 +0800
  • 67a001ea29 modify README.md Blue Liang 2019-12-30 18:58:23 +0800
  • f950c37ce6 add pic dir Blue Liang 2019-12-30 08:54:51 +0800
  • 104d1849c6 add README.en.md content Blue Liang 2019-12-09 13:49:07 +0800
  • e162e68385 add BinToMem_CLI.exe source file liangkangnan 2019-12-08 18:42:15 +0800
  • 2788fb395e fix: tools/BinToMem_CLI.exe can not run on win10 liangkangnan 2019-12-08 18:38:58 +0800
  • ac995f0b01 first release Blue Liang 2019-12-04 08:47:19 +0800
  • aa90d6dd38 Initial commit liangkangnan 2019-12-03 09:53:47 +0800