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Commit Graph

  • ceddc1af24 test:example: move C examples to sdk directory liangkangnan 2020-11-08 22:09:38 +0800
  • 5c9f1a140e rtl: add mem access misaligned exception liangkangnan 2020-11-08 22:08:03 +0800
  • e58ac4e399 README: update Blue Liang 2020-11-05 08:46:44 +0800
  • 9d1f481e85 README: update liangkangnan 2020-10-31 21:16:26 +0800
  • eebfefe33c rtl: gen_buf: add generate name Blue Liang 2020-10-26 17:16:32 +0800
  • 60a4f7d6df rtl: add generate block name Blue Liang 2020-10-26 17:01:04 +0800
  • 6fdf67143c README: update liangkangnan 2020-10-25 14:23:15 +0800
  • 7976a1d7f7 sim: support Linux liangkangnan 2020-10-25 13:49:39 +0800
  • eb5647915a python scripts: remove verison liangkangnan 2020-10-25 12:02:26 +0800
  • 2b44f1e8f3 first release liangkangnan 2020-10-23 21:26:18 +0800
  • 2a6ee067c3 Pre Merge pull request !1 from tanek/master tanek 2020-10-21 21:22:24 +0800
  • acb86e3fc4 README: update liangkangnan 2020-10-21 21:22:04 +0800
  • dac237e5f1 remove build generated files liangkangnan 2020-10-21 21:16:49 +0800
  • 78683179dc use python to implement test scripts liangyongxiang 2020-10-11 03:56:35 +0800
  • b15a130862 sim: compliance_test: add utils modules liangkangnan 2020-10-06 21:00:04 +0800
  • 4876225f60 rtl: utils: add full handshake CDC source liangkangnan 2020-09-23 21:39:20 +0800
  • 386ba909ba rtl: jtag: handle DM module in cpu clock domain liangkangnan 2020-09-23 21:37:00 +0800
  • 633a1d0b15 rtl: debug: fix latch liangkangnan 2020-09-20 22:18:58 +0800
  • 29623c8d2a rtl: div: fix error liangkangnan 2020-09-14 22:22:42 +0800
  • 045f482fe1 rtl: jtag: optimization liangkangnan 2020-09-13 17:47:18 +0800
  • 442e9e8f5c tb: add jtag test result liangkangnan 2020-09-12 14:54:56 +0800
  • 8c3d7ac932 rtl: div: timing optimization liangkangnan 2020-09-12 14:17:34 +0800
  • 90f57951e4 sim: add gen_buf.v liangkangnan 2020-09-12 14:16:02 +0800
  • 8468303ba7 rtl: add gen_buf.v liangkangnan 2020-09-12 14:14:59 +0800
  • b57bfe7736 rtl: timing optimization liangkangnan 2020-09-09 21:00:14 +0800
  • 5e4ab8c33c sim: add gen_dff.v liangkangnan 2020-09-09 20:59:22 +0800
  • a4a723e1e7 rtl: add gen_dff.v liangkangnan 2020-09-09 20:58:08 +0800
  • b6754f002c rtl: div: optimization liangkangnan 2020-09-06 23:17:56 +0800
  • 0ed81ff1a8 rtl: remove unused signals liangkangnan 2020-08-29 22:35:43 +0800
  • 3cd30247d2 tests: example: support sync interrupt handle liangkangnan 2020-08-15 16:09:16 +0800
  • 10a3df3e5a rtl: core: fix sync interrupt liangkangnan 2020-08-15 16:05:06 +0800
  • fccb920070 rtl: core: optimization Blue Liang 2020-08-13 09:01:27 +0800
  • fa958a6153 rtl: rib: arbitrated by logic instead of clock Blue Liang 2020-08-13 08:56:01 +0800
  • 4b5904df81 README: add new plan v2.4 liangkangnan 2020-08-02 21:06:55 +0800
  • e23ad11e7e rtl: fix sync interrupt return address liangkangnan 2020-07-25 22:15:03 +0800
  • b39062a4ea rtl: fix interrupt return address liangkangnan 2020-07-25 16:23:45 +0800
  • 233bb1fb23 fpga: constrs: do not constraint JTAG_CLK clk liangkangnan 2020-07-25 16:20:54 +0800
  • 6e4764f73d example: common.mk: add Makefile dep liangkangnan 2020-07-25 15:24:50 +0800
  • 1ccdeb1b81 example: coremark: fix build error liangkangnan 2020-07-21 22:34:15 +0800
  • b0c4d1fa4d rtl:timer: update interrupt assert liangkangnan 2020-07-12 22:33:15 +0800
  • 6f5fe893cb README: update liangkangnan 2020-07-11 16:09:59 +0800
  • 506abe158f README: update liangkangnan 2020-07-07 23:15:45 +0800
  • 4049559948 fpga: README: update liangkangnan 2020-07-07 23:09:48 +0800
  • 43c3510fc2 README.md: update liangkangnan 2020-07-05 23:03:54 +0800
  • 6642662e71 fpga: add burn mcs file liangkangnan 2020-07-04 22:58:25 +0800
  • 96b2eca546 tb: set uart debug disable liangkangnan 2020-07-04 17:31:58 +0800
  • 15f10fbf35 sim: add uart_debug.v liangkangnan 2020-07-04 17:21:50 +0800
  • f7b3dc8327 fpga: README: add uart download liangkangnan 2020-07-04 16:27:53 +0800
  • ab185de7f5 tools: add uart download script liangkangnan 2020-07-04 14:36:02 +0800
  • 1c51a4e515 README: add uart download liangkangnan 2020-07-04 14:34:46 +0800
  • 8c751095fd fpga: constrs: add uart_debug_en pin liangkangnan 2020-07-04 14:33:33 +0800
  • a73b0ea36b rtl: add uart_debug module liangkangnan 2020-07-04 14:32:31 +0800
  • 4813893a34 sim: compliance_test: compare files line by line Blue Liang 2020-06-28 20:26:12 +0800
  • a945cd1512 pic: update arch.jpg liangkangnan 2020-06-27 10:11:46 +0800
  • 890a6266f3 tests: example: add uart rx liangkangnan 2020-06-26 22:46:03 +0800
  • 1486b5aca8 sim: change uart_tx.v to uart.v liangkangnan 2020-06-26 22:44:14 +0800
  • 317061682d fpga: constrs: add uart rx pin liangkangnan 2020-06-26 22:41:48 +0800
  • 4c6c044afb rtl: add uart rx function liangkangnan 2020-06-26 22:40:44 +0800
  • 405b3fb0c3 tb: add README.md v2.3 liangkangnan 2020-06-21 21:32:10 +0800
  • 193794cf5c README: update liangkangnan 2020-06-21 21:28:07 +0800
  • f2010755bb fpga: constrs: add spi flash config liangkangnan 2020-06-14 22:13:44 +0800
  • 2c8762a102 example: freertos: init gpio mode liangkangnan 2020-06-14 22:06:25 +0800
  • f10a4ac49b example: timer_int: init gpio mode liangkangnan 2020-06-14 22:04:38 +0800
  • 6b01facc48 example: gpio: add input usage liangkangnan 2020-06-14 10:45:55 +0800
  • 5c70814fc6 fpga: constrs: add one more gpio liangkangnan 2020-06-14 10:41:52 +0800
  • 2619f26eae gpio: add input function liangkangnan 2020-06-14 10:40:25 +0800
  • e28381dbcf add support for ebreak inst liangkangnan 2020-06-13 14:56:44 +0800
  • 5f64a5f8ae fpga: update README.md liangkangnan 2020-06-07 21:55:28 +0800
  • 764ecc7199 delete README.en.md liangkangnan 2020-06-07 13:25:14 +0800
  • 5b888bd483 rtl: core: fix data related for csr regs liangkangnan 2020-06-05 22:22:49 +0800
  • 0256674146 compliance test: add rv32Zicsr and rv32Zifencei build liangkangnan 2020-06-05 22:19:49 +0800
  • c3e607ec55 sim: compliance_test: fix can not find ref file liangkangnan 2020-06-05 22:16:36 +0800
  • 69484de8b2 openocd: tinyriscv.cfg: add halt cmd liangkangnan 2020-05-31 21:05:18 +0800
  • de9a978417 fix: must exit openocd after download temporary liangkangnan 2020-05-31 14:41:39 +0800
  • eec414aa96 use = instead of <= liangkangnan 2020-05-31 14:38:57 +0800
  • 1dea4a0a5e fpga: README: exit openocd after download liangkangnan 2020-05-31 12:14:29 +0800
  • 09d45f9ea9 rename FPGA to fpga liangkangnan 2020-05-31 12:05:28 +0800
  • dfbb1ed6c1 sim: compliance_test: add README.md liangkangnan 2020-05-27 23:47:55 +0800
  • 8cb261b079 sim: add README.md liangkangnan 2020-05-27 23:43:35 +0800
  • 0a7d7616ab add new inst test liangkangnan 2020-05-27 23:24:33 +0800
  • 38c2245218 sim: remove tb file to tb dir liangkangnan 2020-05-27 23:17:05 +0800
  • f775abf1d7 sim: add compliance test script liangkangnan 2020-05-27 23:08:43 +0800
  • 362d188458 use tb file in tb dir liangkangnan 2020-05-27 23:07:14 +0800
  • 897a346788 remove .elf liangkangnan 2020-05-27 23:05:39 +0800
  • 7d877c3348 tests: add riscv-compliance liangkangnan 2020-05-27 23:04:07 +0800
  • eb65d0badc FPGA: update simulation settings liangkangnan 2020-05-24 13:37:45 +0800
  • ea0734b280 FPGA: add vivado sim liangkangnan 2020-05-21 22:04:23 +0800
  • edee04cfe2 sim: fix vivado error liangkangnan 2020-05-21 21:53:08 +0800
  • 6c279fee39 update design doc liangkangnan 2020-05-17 23:58:27 +0800
  • ea6656db4d update design doc liangkangnan 2020-05-17 13:47:49 +0800
  • 4d6f7ad664 FPGA: add jtag download liangkangnan 2020-05-13 21:48:44 +0800
  • 834fcfb3ef debug: optimization for jtag liangkangnan 2020-05-13 21:27:40 +0800
  • 260246f488 fix nop inst liangkangnan 2020-05-07 22:40:31 +0800
  • 22ed29a149 add SPI pin liangkangnan 2020-05-06 23:10:42 +0800
  • ae67bfdebe add spi liangkangnan 2020-05-05 19:50:27 +0800
  • 038168c8f2 example: add spi_master liangkangnan 2020-05-05 18:35:33 +0800
  • 86392aa607 add n25q norflash driver liangkangnan 2020-05-05 18:33:50 +0800
  • 27da406793 add spi driver liangkangnan 2020-05-05 18:32:46 +0800
  • 07b33baf94 perips: add spi master liangkangnan 2020-05-05 18:31:08 +0800
  • 837af2c977 use = instead of <= in combination logic liangkangnan 2020-05-02 11:58:44 +0800