Compare commits

...

14 Commits
bram ... master

Author SHA1 Message Date
Blue Liang 86d779f7f3 doc: add first file
Signed-off-by: liangkangnan <liangkangnan@163.com>
2024-07-18 17:54:41 +08:00
Blue Liang 1159d1dd86 README: remove doc link
Signed-off-by: liangkangnan <liangkangnan@163.com>
2024-07-03 10:45:21 +08:00
liangkangnan b24fc9044b update README.md
Signed-off-by: liangkangnan <liangkangnan@163.com>
2022-12-27 09:23:32 +08:00
liangkangnan b1dc8941b2 update README
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-10-16 16:51:04 +08:00
Blue Liang 1ea770ba7e README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-05-21 19:55:56 +08:00
liangkangnan 18dc85e69e README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-01-31 21:39:28 +08:00
liangkangnan 918804fc49 update README
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-01-24 20:39:45 +08:00
Blue Liang e58ac4e399 README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-11-05 08:46:44 +08:00
liangkangnan 9d1f481e85 README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-10-31 21:16:26 +08:00
Blue Liang eebfefe33c rtl: gen_buf: add generate name
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-10-26 17:16:32 +08:00
liangkangnan 6fdf67143c README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-10-25 14:23:15 +08:00
liangkangnan 7976a1d7f7 sim: support Linux
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-10-25 13:49:39 +08:00
liangkangnan acb86e3fc4 README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-10-21 21:22:04 +08:00
liangkangnan dac237e5f1 remove build generated files
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-10-21 21:16:49 +08:00
64 changed files with 361 additions and 195828 deletions

2
.gitignore vendored
View File

@ -2,5 +2,3 @@
*.o
*.ko
*.obj
tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64

View File

@ -1,4 +1,10 @@
与本项目配套的设计文档[《从零开始写RISC-V处理器》](https://liangkangnan.gitee.io/2020/04/29/%E4%BB%8E%E9%9B%B6%E5%BC%80%E5%A7%8B%E5%86%99RISC-V%E5%A4%84%E7%90%86%E5%99%A8/),目前已经更新完第三章硬件篇,开始更新软件篇。
本项目目前一共有3个分支分别是master、bram和verilator分别对应入门、进阶和高级三个级别大家可以根据自身情况选择。
**本项目是一直在更新的verilator分支持续开发中**,如果哪天不再更新了,我会特别说明的。
如果对本项目有疑问或者建议的话,优先通过邮件交流,谢谢。
配套的设计文档在doc目录下目前还没完成
# 1.初衷
@ -32,7 +38,7 @@
**tests**该目录包含测试程序源码其中example目录为C语言程序例程源码isa目录为RV32指令测试源码
**tools**该目录包含编译汇编和C语言程序所需GNU工具链和将二进制文件转成仿真所需的mem格式文件的工具BinToMem还有通过串口下载程序的脚本。BinToMem\_CLI.exe需要在cmd窗口下执行BinToMem\_GUI.exe提供图形界面双击即可运行
**tools**该目录包含编译汇编和C语言程序所需GNU工具链和将二进制文件转成仿真所需的mem格式文件的脚本,还有通过串口下载程序的脚本。
**pic**:存放图片;
@ -54,7 +60,7 @@ tinyriscv目前外挂了6个外设每个外设的空间大小为256MB
![tinyriscv跑分](./pic/tinyriscv_coremark.png)
可知tinyriscv的跑分成绩为2.4。此成绩是基于指令在rom存储和数据在ram存储的情况下得出的如果指令和数据都在ram的话跑分上3.0问题应该不大。
可知tinyriscv的跑分成绩为2.4。
选了几款其他MCU的跑分结果如下图所示
@ -64,9 +70,9 @@ tinyriscv目前外挂了6个外设每个外设的空间大小为256MB
# 4.如何使用
本项目运行在windows平台编译仿真工具使用的是iverilog和vpp波形查看工具使用的是gtkwave。
本项目可以运行在Windows和Linux平台(macOS平台理论上也是可以的)编译仿真工具使用的是iverilog和vpp波形查看工具使用的是gtkwave。
## 4.1安装环境
## 4.1Windows平台环境搭建
在使用之前需要安装以下工具:
@ -88,15 +94,61 @@ tinyriscv目前外挂了6个外设每个外设的空间大小为256MB
到[python官网](https://www.python.org/)下载win版本的python注意要下载python3版本的。网速慢的同学可以通过百度网盘下载(链接: https://pan.baidu.com/s/1gNC8L5dZTsN6E5TJD2rmnQ 提取码: 3b4t),或者通过微云下载[https://share.weiyun.com/XwzSQHND](https://share.weiyun.com/XwzSQHND)。安装完后将python添加到环境变量里。
5. 下载代码
5. 下载tinyriscv代码
使用git clone命令下载不要使用zip方式下载否则有些文件会有格式问题。
**使用git clone命令下载不要使用zip方式下载**,否则有些文件会有格式问题。
`git clone https://gitee.com/liangkangnan/tinyriscv.git`
## 4.2运行指令测试程序
## 4.2Linux平台环境搭建
### 4.2.1 运行旧的指令测试程序
这里以Ubuntu系统为例进行说明。
1. 下载iverilog源码
`git clone https://github.com/steveicarus/iverilog.git`
2. 切换到v11分支(必须用V11或以上的版本)
`git checkout v11-branch`
3. 安装依赖
`sudo apt-get install autoconf gperf flex bison build-essential`
4. 编译、安装iverilog和vvp
```
sh autoconf.sh
./configure
make
make install
```
5. 创建python软链接
`sudo ln -s /usr/bin/python3.8 /usr/bin/python`
其中/usr/bin/python3.8对应你实际安装的python版本。
6. 安装gtkwave
`sudo apt-get install gtkwave`
7. 安装GNU工具链
可以从百度网盘下载(链接https://pan.baidu.com/s/10uLZYf_cgtH94kZI_N6JhQ
提取码uk0w)或者自行下载其他版本的下载后解压到tools目录下。
最后需要确认tests/example/common.mk文件里的这几行内容要与你安装的工具链对应得上。
![toolchain](./pic/toolchain.png)
## 4.3运行指令测试程序
这里以Windows平台为例进行说明Linux平台是类似的。
### 4.3.1 运行旧的指令测试程序
旧的指令测试程序属于比较早的指令兼容性测试方法虽然目前RISC-V官方已经不更新了但仍然是一个比较好的测试参考。
@ -104,7 +156,7 @@ tinyriscv目前外挂了6个外设每个外设的空间大小为256MB
打开CMD窗口进入到sim目录执行以下命令
```sim_new_nowave.bat ..\tests\isa\generated\rv32ui-p-add.bin inst.data```
```python .\sim_new_nowave.py ..\tests\isa\generated\rv32ui-p-add.bin inst.data```
如果运行成功的话就可以看到&quot;PASS&quot;的打印。其他指令使用方法类似。
@ -116,7 +168,7 @@ tinyriscv目前外挂了6个外设每个外设的空间大小为256MB
`python .\test_all_isa.py`
### 4.2.2运行新的指令测试程序
### 4.3.2运行新的指令测试程序
新的指令兼容性([riscv-compliance](https://github.com/riscv/riscv-compliance))测试项相对于旧的指令兼容性测试项来说对指令的测试更加严谨可以精确到每一条指令的运行结果而且RISC-V官方一直在更新。
@ -124,29 +176,25 @@ tinyriscv目前外挂了6个外设每个外设的空间大小为256MB
打开CMD窗口进入到sim/compliance_test目录执行以下命令
`python compliance_test.py ..\..\tests\riscv-compliance\build_generated\rv32i\I-ADD-01.elf.bin inst.data`
`python .\compliance_test.py ..\..\tests\riscv-compliance\build_generated\rv32i\I-ADD-01.elf.bin inst.data`
如果运行成功的话就可以看到&quot;PASS&quot;的打印。其他指令使用方法类似。
![new_test_output](./pic/new_test_output.png)
## 4.3运行C语言程序
## 4.4运行C语言程序
C语言程序例程位于tests\example目录里。
下面以simple程序为例进行说明。
首先打开CMD窗口进入到tests\example\simple目录执行以下命令清除旧的目标文件
`make clean`
然后重新编译:
打开CMD窗口进入到tests\example\simple目录执行以下命令编译
`make`
编译成功之后进入到sim目录执行以下命令开始测试
` .\sim_new_nowave.bat ..\tests\example\simple\simple.bin inst.data`
` python .\sim_new_nowave.py ..\tests\example\simple\simple.bin inst.data`
# 5.移植到FPGA
@ -161,6 +209,8 @@ C语言程序例程位于tests\example目录里。
# 7.更新记录
2020-10-25支持Linux平台编译、仿真。新建bram分支使用BRAM代替LUTRAM(DRAM)节省一半以上的LUT资源并且可以运行更大的程序。
2020-07-04支持通过UART烧写固件
2020-05-27增加新的指令兼容性(riscv-compliance)测试项。
@ -197,7 +247,5 @@ C语言程序例程位于tests\example目录里。
# 8.其他
如有疑问或者建议,欢迎在下方评论、或者私信、或者发邮件(liangkangnan@163.com)给我24小时内必回复。
如果您热爱RISC-V或者对RISC-V感兴趣欢迎发邮件或者私信我我把您拉进群里面交流RISC-V相关的技术。
如有疑问或者建议,欢迎私信或者发邮件(liangkangnan@163.com)给我。

Binary file not shown.

Binary file not shown.

Before

Width:  |  Height:  |  Size: 12 KiB

After

Width:  |  Height:  |  Size: 16 KiB

Binary file not shown.

Before

Width:  |  Height:  |  Size: 68 KiB

After

Width:  |  Height:  |  Size: 29 KiB

BIN
pic/toolchain.png Normal file

Binary file not shown.

After

Width:  |  Height:  |  Size: 33 KiB

View File

@ -32,10 +32,10 @@ module gen_ticks_sync #(
genvar i;
generate
for (i = 0; i < DP; i = i + 1) begin
if (i == 0) begin
for (i = 0; i < DP; i = i + 1) begin: dp_width
if (i == 0) begin: dp_is_0
gen_rst_0_dff #(DW) rst_0_dff(clk, rst, din, sync_dat[0]);
end else begin
end else begin: dp_is_not_0
gen_rst_0_dff #(DW) rst_0_dff(clk, rst, sync_dat[i-1], sync_dat[i]);
end
end

8
sim/.gitignore vendored Normal file
View File

@ -0,0 +1,8 @@
# Object files
*.o
*.ko
*.obj
inst.data
out.vvp
tinyriscv_soc_tb.vcd

View File

@ -1,22 +1,40 @@
# sim_new_nowave.bat
# compile_rtl.py
编译rtl代码。
使用方法:
`python compile_rtl.py [rtl目录相对路径]`
比如:
`python compile_rtl.py ..`
# sim_new_nowave.py
对指定的bin文件(重新生成inst.data文件)进行测试。
使用方法:
`sim_new_nowave.bat ..\tests\isa\generated\rv32ui-p-add.bin inst.data`
windows系统下
# sim_default_nowave.bat
`python sim_new_nowave.py ..\tests\isa\generated\rv32ui-p-add.bin inst.data`
Linux系统下
`python sim_new_nowave.py ../tests/isa/generated/rv32ui-p-add.bin inst.data`
# sim_default_nowave.py
对已经存在的inst.data文件进行测试。
使用方法:
`sim_default_nowave.bat`
`python sim_default_nowave.py`
# test_all_isa.py
一次性测试所有指令。
一次性测试../tests/isa/generated目录下的所有指令。
使用方法:

68
sim/compile_rtl.py Normal file
View File

@ -0,0 +1,68 @@
import sys
import filecmp
import subprocess
import sys
import os
# 主函数
def main():
rtl_dir = sys.argv[1]
if rtl_dir != r'..':
tb_file = r'/tb/compliance_test/tinyriscv_soc_tb.v'
else:
tb_file = r'/tb/tinyriscv_soc_tb.v'
# iverilog程序
iverilog_cmd = ['iverilog']
# 顶层模块
#iverilog_cmd += ['-s', r'tinyriscv_soc_tb']
# 编译生成文件
iverilog_cmd += ['-o', r'out.vvp']
# 头文件(defines.v)路径
iverilog_cmd += ['-I', rtl_dir + r'/rtl/core']
# 宏定义,仿真输出文件
iverilog_cmd += ['-D', r'OUTPUT="signature.output"']
# testbench文件
iverilog_cmd.append(rtl_dir + tb_file)
# ../rtl/core
iverilog_cmd.append(rtl_dir + r'/rtl/core/clint.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/csr_reg.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/ctrl.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/defines.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/div.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/ex.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/id.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/id_ex.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/if_id.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/pc_reg.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/regs.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/rib.v')
iverilog_cmd.append(rtl_dir + r'/rtl/core/tinyriscv.v')
# ../rtl/perips
iverilog_cmd.append(rtl_dir + r'/rtl/perips/ram.v')
iverilog_cmd.append(rtl_dir + r'/rtl/perips/rom.v')
iverilog_cmd.append(rtl_dir + r'/rtl/perips/timer.v')
iverilog_cmd.append(rtl_dir + r'/rtl/perips/uart.v')
iverilog_cmd.append(rtl_dir + r'/rtl/perips/gpio.v')
iverilog_cmd.append(rtl_dir + r'/rtl/perips/spi.v')
# ../rtl/debug
iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_dm.v')
iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_driver.v')
iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_top.v')
iverilog_cmd.append(rtl_dir + r'/rtl/debug/uart_debug.v')
# ../rtl/soc
iverilog_cmd.append(rtl_dir + r'/rtl/soc/tinyriscv_soc_top.v')
# ../rtl/utils
iverilog_cmd.append(rtl_dir + r'/rtl/utils/full_handshake_rx.v')
iverilog_cmd.append(rtl_dir + r'/rtl/utils/full_handshake_tx.v')
iverilog_cmd.append(rtl_dir + r'/rtl/utils/gen_buf.v')
iverilog_cmd.append(rtl_dir + r'/rtl/utils/gen_dff.v')
# 编译
process = subprocess.Popen(iverilog_cmd)
process.wait(timeout=5)
if __name__ == '__main__':
sys.exit(main())

11
sim/compliance_test/.gitignore vendored Normal file
View File

@ -0,0 +1,11 @@
# Object files
*.o
*.ko
*.obj
inst.data
out.vvp
tinyriscv_soc_tb.vcd
complie.log
run.log
signature.output

View File

@ -2,4 +2,10 @@
使用方法:
Windows系统下
`python compliance_test.py ..\..\tests\riscv-compliance\build_generated\rv32i\I-ADD-01.elf.bin inst.data`
Linux系统下
`python compliance_test.py ../../tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.bin inst.data`

View File

@ -1,57 +1,10 @@
import sys
import filecmp
import subprocess
import sys
import os
# iverilog程序
iverilog_cmd = ['iverilog']
# 顶层模块
#iverilog_cmd += ['-s', r'tinyriscv_soc_tb']
# 编译生成文件
iverilog_cmd += ['-o', r'out.vvp']
# 头文件(defines.v)路径
iverilog_cmd += ['-I', r'..\..\rtl\core']
# 宏定义,仿真输出文件
iverilog_cmd += ['-D', r'OUTPUT="signature.output"']
# testbench文件
iverilog_cmd.append(r'..\..\tb\compliance_test\tinyriscv_soc_tb.v')
# ..\rtl\core
iverilog_cmd.append(r'..\..\rtl\core\defines.v')
iverilog_cmd.append(r'..\..\rtl\core\ex.v')
iverilog_cmd.append(r'..\..\rtl\core\id.v')
iverilog_cmd.append(r'..\..\rtl\core\tinyriscv.v')
iverilog_cmd.append(r'..\..\rtl\core\pc_reg.v')
iverilog_cmd.append(r'..\..\rtl\core\id_ex.v')
iverilog_cmd.append(r'..\..\rtl\core\ctrl.v')
iverilog_cmd.append(r'..\..\rtl\core\regs.v')
iverilog_cmd.append(r'..\..\rtl\core\if_id.v')
iverilog_cmd.append(r'..\..\rtl\core\div.v')
iverilog_cmd.append(r'..\..\rtl\core\rib.v')
iverilog_cmd.append(r'..\..\rtl\core\clint.v')
iverilog_cmd.append(r'..\..\rtl\core\csr_reg.v')
# ..\rtl\perips
iverilog_cmd.append(r'..\..\rtl\perips\ram.v')
iverilog_cmd.append(r'..\..\rtl\perips\rom.v')
iverilog_cmd.append(r'..\..\rtl\perips\spi.v')
iverilog_cmd.append(r'..\..\rtl\perips\timer.v')
iverilog_cmd.append(r'..\..\rtl\perips\uart.v')
iverilog_cmd.append(r'..\..\rtl\perips\gpio.v')
# ..\rtl\debug
iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v')
iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v')
iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v')
iverilog_cmd.append(r'..\..\rtl\debug\uart_debug.v')
# ..rtl\utils
iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_rx.v')
iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_tx.v')
iverilog_cmd.append(r'..\..\rtl\utils\gen_buf.v')
iverilog_cmd.append(r'..\..\rtl\utils\gen_dff.v')
# ..\rtl\soc
iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')
# 找出path目录下的所有reference_output文件
def list_ref_files(path):
files = []
@ -74,13 +27,13 @@ def get_reference_file(bin_file):
files = []
if (bin_file.find('rv32im') != -1):
files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32im\references')
files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32im/references')
elif (bin_file.find('rv32i') != -1):
files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32i\references')
files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32i/references')
elif (bin_file.find('rv32Zicsr') != -1):
files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zicsr\references')
files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references')
elif (bin_file.find('rv32Zifencei') != -1):
files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zifencei\references')
files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32Zifencei/references')
else:
return None
@ -96,17 +49,14 @@ def main():
#print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
# 1.将bin文件转成mem文件
bin_to_mem_cmd = [r'..\..\tools\BinToMem_CLI.exe']
bin_to_mem_cmd.append(sys.argv[1])
bin_to_mem_cmd.append(sys.argv[2])
process = subprocess.Popen(bin_to_mem_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
process.wait(timeout=5)
cmd = r'python ../../tools/BinToMem_CLI.py' + ' ' + sys.argv[1] + ' ' + sys.argv[2]
f = os.popen(cmd)
f.close()
# 2.编译rtl文件
logfile = open('complie.log', 'w')
process = subprocess.Popen(iverilog_cmd, stdout=logfile, stderr=logfile)
process.wait(timeout=5)
logfile.close()
cmd = r'python ../compile_rtl.py' + r' ../..'
f = os.popen(cmd)
f.close()
# 3.运行
logfile = open('run.log', 'w')
@ -121,7 +71,7 @@ def main():
if (ref_file != None):
# 如果文件大小不一致直接报fail
if (os.path.getsize('signature.output') != os.path.getsize(ref_file)):
print('!!! FAIL !!!')
print('!!! FAIL, size != !!!')
return
f1 = open('signature.output')
f2 = open(ref_file)
@ -131,7 +81,7 @@ def main():
for line in f2.readlines():
# 只要有一行内容不一样就报fail
if (f1_lines[i] != line):
print('!!! FAIL !!!')
print('!!! FAIL, content != !!!')
f1.close()
f2.close()
return
@ -142,6 +92,5 @@ def main():
else:
print('No ref file found, please check result by yourself.')
if __name__ == '__main__':
sys.exit(main())

File diff suppressed because it is too large Load Diff

File diff suppressed because one or more lines are too long

View File

@ -1,3 +0,0 @@
test running...
WARNING: ..\..\tb\compliance_test\tinyriscv_soc_tb.v:502: $readmemh(inst.data): Not enough words in the file for the requested range [0:4095].
VCD info: dumpfile tinyriscv_soc_tb.vcd opened for output.

View File

@ -1,36 +0,0 @@
00000000
fffff802
ffffffff
fffff5cb
80000000
00001a34
07654320
80000000
80000000
07654320
00001a34
80000000
fffff5cb
fffffffe
fffff802
00000000
ffffffff
fffff802
ffffffff
fffff5cb
80000000
00001a34
07654320
80000000
80000000
07654320
00001a34
80000000
fffff5cb
fffffffe
fffff802
00000000
ffffffff
ffffffff
ffffffff
00000000

File diff suppressed because it is too large Load Diff

View File

@ -1,182 +0,0 @@
10001197
80018193
10002117
ff810113
00000d13
00000d93
2d800513
10000597
fe458593
10000617
fdc60613
00c5fc63
00052283
0055a023
00450513
00458593
fec5e8e3
10000517
fbc50513
80818593
00b57863
00052023
00450513
feb56ce3
250000ef
10c000ef
00100d13
0000006f
f8010113
00112223
00212423
00312623
00412823
00512a23
00612c23
00712e23
02812023
02912223
02a12423
02b12623
02c12823
02d12a23
02e12c23
02f12e23
05012023
05112223
05212423
05312623
05412823
05512a23
05612c23
05712e23
07812023
07912223
07c12823
07d12a23
07e12c23
07f12e23
34202573
198000ef
00412083
00812103
00c12183
01012203
01412283
01812303
01c12383
02012403
02412483
02812503
02c12583
03012603
03412683
03812703
03c12783
04012803
04412883
04812903
04c12983
05012a03
05412a83
05812b03
05c12b83
06012c03
06412c83
07012e03
07412e83
07812f03
07c12f83
08010113
30200073
0000006f
ff010113
00812623
01010413
10000797
e8478793
0007a023
10000797
e7c78793
00078023
200007b7
00878793
1f400713
00e7a023
200007b7
00700713
00e7a023
10000797
e5478793
0007c783
0ff7f793
fe0788e3
200007b7
0007a703
200007b7
00176713
00e7a023
10000797
e2c78793
00078023
10000797
e1c78793
0007a783
00178713
10000797
e0c78793
00e7a023
10000797
e0078793
0007a703
00200793
faf710e3
200007b7
0007a023
10000797
de478793
0007a023
00100d93
00000013
00000793
00078513
00c12403
01010113
00008067
ff010113
00812623
01010413
200007b7
0007a703
200007b7
00476713
00e7a023
10000797
da078793
00100713
00e78023
00000013
00c12403
01010113
00008067
fe010113
00112e23
00812c23
02010413
fea42623
fadff0ef
00000013
01c12083
01812403
02010113
00008067
ff010113
00812623
01010413
00000797
db478793
30579073
00000013
00c12403
01010113
00008067

13768
sim/out.vvp

File diff suppressed because one or more lines are too long

View File

@ -1,2 +0,0 @@
iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\utils\full_handshake_rx.v ..\rtl\utils\full_handshake_tx.v ..\rtl\soc\tinyriscv_soc_top.v
vvp out.vvp

28
sim/sim_default_nowave.py Normal file
View File

@ -0,0 +1,28 @@
import sys
import filecmp
import subprocess
import sys
import os
# 主函数
def main():
#print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
# 1.编译rtl文件
cmd = r'python compile_rtl.py' + r' ..'
f = os.popen(cmd)
f.close()
# 2.运行
vvp_cmd = [r'vvp']
vvp_cmd.append(r'out.vvp')
process = subprocess.Popen(vvp_cmd)
try:
process.wait(timeout=10)
except subprocess.TimeoutExpired:
print('!!!Fail, vvp exec timeout!!!')
if __name__ == '__main__':
sys.exit(main())

View File

@ -1,3 +0,0 @@
..\tools\BinToMem_CLI.exe %1 %2
iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\utils\full_handshake_rx.v ..\rtl\utils\full_handshake_tx.v ..\rtl\soc\tinyriscv_soc_top.v
vvp out.vvp

33
sim/sim_new_nowave.py Normal file
View File

@ -0,0 +1,33 @@
import sys
import filecmp
import subprocess
import sys
import os
# 主函数
def main():
#print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
# 1.将bin文件转成mem文件
cmd = r'python ../tools/BinToMem_CLI.py' + ' ' + sys.argv[1] + ' ' + sys.argv[2]
f = os.popen(cmd)
f.close()
# 2.编译rtl文件
cmd = r'python compile_rtl.py' + r' ..'
f = os.popen(cmd)
f.close()
# 3.运行
vvp_cmd = [r'vvp']
vvp_cmd.append(r'out.vvp')
process = subprocess.Popen(vvp_cmd)
try:
process.wait(timeout=20)
except subprocess.TimeoutExpired:
print('!!!Fail, vvp exec timeout!!!')
if __name__ == '__main__':
sys.exit(main())

View File

@ -1,4 +1,7 @@
import os
import subprocess
import sys
# 找出path目录下的所有bin文件
def list_binfiles(path):
@ -12,16 +15,16 @@ def list_binfiles(path):
return files
# 主函数
def main():
bin_files = list_binfiles(r'../tests/isa/generated')
files = list_binfiles('..\\tests\\isa\\generated')
anyfail = False
anyfail = False
# 对每一个bin文件进行测试
for file in files:
# 对每一个bin文件进行测试
for file in bin_files:
#print(file)
cmd = '.\\sim_new_nowave.bat ' + file + ' inst.data'
cmd = r'python sim_new_nowave.py' + ' ' + file + ' ' + 'inst.data'
f = os.popen(cmd)
r = f.read()
f.close()
@ -32,5 +35,9 @@ for file in files:
anyfail = True
break
if (anyfail == False):
if (anyfail == False):
print('Congratulation, All PASS...')
if __name__ == '__main__':
sys.exit(main())

File diff suppressed because it is too large Load Diff

4
tests/example/.gitignore vendored Normal file
View File

@ -0,0 +1,4 @@
# Object files
*.o
*.ko
*.obj

View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
freertos.bin
freertos.dump
freertos

File diff suppressed because it is too large Load Diff

7
tests/example/coremark/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
coremark.bin
coremark.dump
coremark

Binary file not shown.

Binary file not shown.

File diff suppressed because it is too large Load Diff

7
tests/example/gpio/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
gpio.bin
gpio.dump
gpio

Binary file not shown.

Binary file not shown.

View File

@ -1,265 +0,0 @@
gpio: file format elf32-littleriscv
Disassembly of section .init:
00000000 <_start>:
0: 10001197 auipc gp,0x10001
4: 80018193 addi gp,gp,-2048 # 10000800 <__global_pointer$>
8: 10002117 auipc sp,0x10002
c: ff810113 addi sp,sp,-8 # 10002000 <_sp>
10: 34000513 li a0,832
14: 10000597 auipc a1,0x10000
18: fec58593 addi a1,a1,-20 # 10000000 <__bss_start>
1c: 10000617 auipc a2,0x10000
20: fe460613 addi a2,a2,-28 # 10000000 <__bss_start>
24: 00c5fc63 bgeu a1,a2,3c <_start+0x3c>
28: 00052283 lw t0,0(a0)
2c: 0055a023 sw t0,0(a1)
30: 00450513 addi a0,a0,4
34: 00458593 addi a1,a1,4
38: fec5e8e3 bltu a1,a2,28 <_start+0x28>
3c: 10000517 auipc a0,0x10000
40: fc450513 addi a0,a0,-60 # 10000000 <__bss_start>
44: 10000597 auipc a1,0x10000
48: fbc58593 addi a1,a1,-68 # 10000000 <__bss_start>
4c: 00b57863 bgeu a0,a1,5c <_start+0x5c>
50: 00052023 sw zero,0(a0)
54: 00450513 addi a0,a0,4
58: feb56ce3 bltu a0,a1,50 <_start+0x50>
5c: 188000ef jal ra,1e4 <_init>
60: 118000ef jal ra,178 <main>
00000064 <loop>:
64: 0000006f j 64 <loop>
Disassembly of section .text:
00000068 <trap_entry>:
68: f8010113 addi sp,sp,-128
6c: 00112223 sw ra,4(sp)
70: 00212423 sw sp,8(sp)
74: 00312623 sw gp,12(sp)
78: 00412823 sw tp,16(sp)
7c: 00512a23 sw t0,20(sp)
80: 00612c23 sw t1,24(sp)
84: 00712e23 sw t2,28(sp)
88: 02812023 sw s0,32(sp)
8c: 02912223 sw s1,36(sp)
90: 02a12423 sw a0,40(sp)
94: 02b12623 sw a1,44(sp)
98: 02c12823 sw a2,48(sp)
9c: 02d12a23 sw a3,52(sp)
a0: 02e12c23 sw a4,56(sp)
a4: 02f12e23 sw a5,60(sp)
a8: 05012023 sw a6,64(sp)
ac: 05112223 sw a7,68(sp)
b0: 05212423 sw s2,72(sp)
b4: 05312623 sw s3,76(sp)
b8: 05412823 sw s4,80(sp)
bc: 05512a23 sw s5,84(sp)
c0: 05612c23 sw s6,88(sp)
c4: 05712e23 sw s7,92(sp)
c8: 07812023 sw s8,96(sp)
cc: 07912223 sw s9,100(sp)
d0: 07a12423 sw s10,104(sp)
d4: 07b12623 sw s11,108(sp)
d8: 07c12823 sw t3,112(sp)
dc: 07d12a23 sw t4,116(sp)
e0: 07e12c23 sw t5,120(sp)
e4: 07f12e23 sw t6,124(sp)
e8: 34202573 csrr a0,mcause
ec: 0c8000ef jal ra,1b4 <trap_handler>
f0: 00412083 lw ra,4(sp)
f4: 00812103 lw sp,8(sp)
f8: 00c12183 lw gp,12(sp)
fc: 01012203 lw tp,16(sp)
100: 01412283 lw t0,20(sp)
104: 01812303 lw t1,24(sp)
108: 01c12383 lw t2,28(sp)
10c: 02012403 lw s0,32(sp)
110: 02412483 lw s1,36(sp)
114: 02812503 lw a0,40(sp)
118: 02c12583 lw a1,44(sp)
11c: 03012603 lw a2,48(sp)
120: 03412683 lw a3,52(sp)
124: 03812703 lw a4,56(sp)
128: 03c12783 lw a5,60(sp)
12c: 04012803 lw a6,64(sp)
130: 04412883 lw a7,68(sp)
134: 04812903 lw s2,72(sp)
138: 04c12983 lw s3,76(sp)
13c: 05012a03 lw s4,80(sp)
140: 05412a83 lw s5,84(sp)
144: 05812b03 lw s6,88(sp)
148: 05c12b83 lw s7,92(sp)
14c: 06012c03 lw s8,96(sp)
150: 06412c83 lw s9,100(sp)
154: 06812d03 lw s10,104(sp)
158: 06c12d83 lw s11,108(sp)
15c: 07012e03 lw t3,112(sp)
160: 07412e83 lw t4,116(sp)
164: 07812f03 lw t5,120(sp)
168: 07c12f83 lw t6,124(sp)
16c: 08010113 addi sp,sp,128
170: 30200073 mret
174: 0000006f j 174 <trap_entry+0x10c>
00000178 <main>:
178: ff010113 addi sp,sp,-16
17c: 00112623 sw ra,12(sp)
180: 00812423 sw s0,8(sp)
184: 01010413 addi s0,sp,16
188: 400007b7 lui a5,0x40000
18c: 00478793 addi a5,a5,4 # 40000004 <_sp+0x2fffe004>
190: 0007a703 lw a4,0(a5)
194: 400007b7 lui a5,0x40000
198: 00478793 addi a5,a5,4 # 40000004 <_sp+0x2fffe004>
19c: 00174713 xori a4,a4,1
1a0: 00e7a023 sw a4,0(a5)
1a4: 0007a7b7 lui a5,0x7a
1a8: 12078513 addi a0,a5,288 # 7a120 <__stack_size+0x79920>
1ac: 0e0000ef jal ra,28c <busy_wait>
1b0: fd9ff06f j 188 <main+0x10>
000001b4 <trap_handler>:
1b4: fe010113 addi sp,sp,-32
1b8: 00112e23 sw ra,28(sp)
1bc: 00812c23 sw s0,24(sp)
1c0: 02010413 addi s0,sp,32
1c4: fea42623 sw a0,-20(s0)
1c8: 00000097 auipc ra,0x0
1cc: 000000e7 jalr zero # 0 <_start>
1d0: 00000013 nop
1d4: 01c12083 lw ra,28(sp)
1d8: 01812403 lw s0,24(sp)
1dc: 02010113 addi sp,sp,32
1e0: 00008067 ret
000001e4 <_init>:
1e4: ff010113 addi sp,sp,-16
1e8: 00812623 sw s0,12(sp)
1ec: 01010413 addi s0,sp,16
1f0: 00000797 auipc a5,0x0
1f4: e7878793 addi a5,a5,-392 # 68 <trap_entry>
1f8: 30579073 csrw mtvec,a5
1fc: 00000013 nop
200: 00c12403 lw s0,12(sp)
204: 01010113 addi sp,sp,16
208: 00008067 ret
0000020c <get_cycle_value>:
20c: fd010113 addi sp,sp,-48
210: 02812623 sw s0,44(sp)
214: 03010413 addi s0,sp,48
218: c0002773 rdcycle a4
21c: fee42623 sw a4,-20(s0)
220: fec42703 lw a4,-20(s0)
224: fee42023 sw a4,-32(s0)
228: fe042223 sw zero,-28(s0)
22c: c8002773 rdcycleh a4
230: fce42e23 sw a4,-36(s0)
234: fdc42703 lw a4,-36(s0)
238: 00070793 mv a5,a4
23c: 00000813 li a6,0
240: 00079613 slli a2,a5,0x0
244: 00000593 li a1,0
248: fe042683 lw a3,-32(s0)
24c: fe442703 lw a4,-28(s0)
250: 00b687b3 add a5,a3,a1
254: 00078513 mv a0,a5
258: 00d53533 sltu a0,a0,a3
25c: 00c70833 add a6,a4,a2
260: 01050733 add a4,a0,a6
264: 00070813 mv a6,a4
268: fef42023 sw a5,-32(s0)
26c: ff042223 sw a6,-28(s0)
270: fe042783 lw a5,-32(s0)
274: fe442803 lw a6,-28(s0)
278: 00078513 mv a0,a5
27c: 00080593 mv a1,a6
280: 02c12403 lw s0,44(sp)
284: 03010113 addi sp,sp,48
288: 00008067 ret
0000028c <busy_wait>:
28c: fd010113 addi sp,sp,-48
290: 02112623 sw ra,44(sp)
294: 02812423 sw s0,40(sp)
298: 03212223 sw s2,36(sp)
29c: 03312023 sw s3,32(sp)
2a0: 03010413 addi s0,sp,48
2a4: fca42e23 sw a0,-36(s0)
2a8: fdc42703 lw a4,-36(s0)
2ac: 03200793 li a5,50
2b0: 02f707b3 mul a5,a4,a5
2b4: fef42623 sw a5,-20(s0)
2b8: f55ff0ef jal ra,20c <get_cycle_value>
2bc: fea42023 sw a0,-32(s0)
2c0: feb42223 sw a1,-28(s0)
2c4: 00000013 nop
2c8: f45ff0ef jal ra,20c <get_cycle_value>
2cc: 00058613 mv a2,a1
2d0: 00050593 mv a1,a0
2d4: fec42783 lw a5,-20(s0)
2d8: 00078913 mv s2,a5
2dc: 00000993 li s3,0
2e0: fe042683 lw a3,-32(s0)
2e4: fe442703 lw a4,-28(s0)
2e8: 00d907b3 add a5,s2,a3
2ec: 00078513 mv a0,a5
2f0: 01253533 sltu a0,a0,s2
2f4: 00e98833 add a6,s3,a4
2f8: 01050733 add a4,a0,a6
2fc: 00070813 mv a6,a4
300: 00080693 mv a3,a6
304: 00060713 mv a4,a2
308: fcd760e3 bltu a4,a3,2c8 <busy_wait+0x3c>
30c: 00080693 mv a3,a6
310: 00060713 mv a4,a2
314: 00e69863 bne a3,a4,324 <busy_wait+0x98>
318: 00078713 mv a4,a5
31c: 00058793 mv a5,a1
320: fae7e4e3 bltu a5,a4,2c8 <busy_wait+0x3c>
324: 00000013 nop
328: 02c12083 lw ra,44(sp)
32c: 02812403 lw s0,40(sp)
330: 02412903 lw s2,36(sp)
334: 02012983 lw s3,32(sp)
338: 03010113 addi sp,sp,48
33c: 00008067 ret
Disassembly of section .stack:
10001800 <_sp-0x800>:
...
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <trap_entry+0x48>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <trap_entry+0x54>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...

4
tests/example/lib/.gitignore vendored Normal file
View File

@ -0,0 +1,4 @@
# Object files
*.o
*.ko
*.obj

7
tests/example/simple/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
simple.bin
simple.dump
simple

Binary file not shown.

Binary file not shown.

View File

@ -1,229 +0,0 @@
simple: file format elf32-littleriscv
Disassembly of section .init:
00000000 <_start>:
0: 10001197 auipc gp,0x10001
4: 80018193 addi gp,gp,-2048 # 10000800 <__global_pointer$>
8: 10002117 auipc sp,0x10002
c: ff810113 addi sp,sp,-8 # 10002000 <_sp>
10: 00000d13 li s10,0
14: 00000d93 li s11,0
18: 2a000513 li a0,672
1c: 10000597 auipc a1,0x10000
20: fe458593 addi a1,a1,-28 # 10000000 <_data>
24: 80818613 addi a2,gp,-2040 # 10000008 <__bss_start>
28: 00c5fc63 bgeu a1,a2,40 <_start+0x40>
2c: 00052283 lw t0,0(a0)
30: 0055a023 sw t0,0(a1)
34: 00450513 addi a0,a0,4
38: 00458593 addi a1,a1,4
3c: fec5e8e3 bltu a1,a2,2c <_start+0x2c>
40: 80818513 addi a0,gp,-2040 # 10000008 <__bss_start>
44: 80818593 addi a1,gp,-2040 # 10000008 <__bss_start>
48: 00b57863 bgeu a0,a1,58 <_start+0x58>
4c: 00052023 sw zero,0(a0)
50: 00450513 addi a0,a0,4
54: feb56ce3 bltu a0,a1,4c <_start+0x4c>
58: 220000ef jal ra,278 <_init>
5c: 10c000ef jal ra,168 <main>
60: 00100d13 li s10,1
00000064 <loop>:
64: 0000006f j 64 <loop>
Disassembly of section .text:
00000068 <trap_entry>:
68: f8010113 addi sp,sp,-128
6c: 00112223 sw ra,4(sp)
70: 00212423 sw sp,8(sp)
74: 00312623 sw gp,12(sp)
78: 00412823 sw tp,16(sp)
7c: 00512a23 sw t0,20(sp)
80: 00612c23 sw t1,24(sp)
84: 00712e23 sw t2,28(sp)
88: 02812023 sw s0,32(sp)
8c: 02912223 sw s1,36(sp)
90: 02a12423 sw a0,40(sp)
94: 02b12623 sw a1,44(sp)
98: 02c12823 sw a2,48(sp)
9c: 02d12a23 sw a3,52(sp)
a0: 02e12c23 sw a4,56(sp)
a4: 02f12e23 sw a5,60(sp)
a8: 05012023 sw a6,64(sp)
ac: 05112223 sw a7,68(sp)
b0: 05212423 sw s2,72(sp)
b4: 05312623 sw s3,76(sp)
b8: 05412823 sw s4,80(sp)
bc: 05512a23 sw s5,84(sp)
c0: 05612c23 sw s6,88(sp)
c4: 05712e23 sw s7,92(sp)
c8: 07812023 sw s8,96(sp)
cc: 07912223 sw s9,100(sp)
d0: 07c12823 sw t3,112(sp)
d4: 07d12a23 sw t4,116(sp)
d8: 07e12c23 sw t5,120(sp)
dc: 07f12e23 sw t6,124(sp)
e0: 34202573 csrr a0,mcause
e4: 164000ef jal ra,248 <trap_handler>
e8: 00412083 lw ra,4(sp)
ec: 00812103 lw sp,8(sp)
f0: 00c12183 lw gp,12(sp)
f4: 01012203 lw tp,16(sp)
f8: 01412283 lw t0,20(sp)
fc: 01812303 lw t1,24(sp)
100: 01c12383 lw t2,28(sp)
104: 02012403 lw s0,32(sp)
108: 02412483 lw s1,36(sp)
10c: 02812503 lw a0,40(sp)
110: 02c12583 lw a1,44(sp)
114: 03012603 lw a2,48(sp)
118: 03412683 lw a3,52(sp)
11c: 03812703 lw a4,56(sp)
120: 03c12783 lw a5,60(sp)
124: 04012803 lw a6,64(sp)
128: 04412883 lw a7,68(sp)
12c: 04812903 lw s2,72(sp)
130: 04c12983 lw s3,76(sp)
134: 05012a03 lw s4,80(sp)
138: 05412a83 lw s5,84(sp)
13c: 05812b03 lw s6,88(sp)
140: 05c12b83 lw s7,92(sp)
144: 06012c03 lw s8,96(sp)
148: 06412c83 lw s9,100(sp)
14c: 07012e03 lw t3,112(sp)
150: 07412e83 lw t4,116(sp)
154: 07812f03 lw t5,120(sp)
158: 07c12f83 lw t6,124(sp)
15c: 08010113 addi sp,sp,128
160: 30200073 mret
164: 0000006f j 164 <trap_entry+0xfc>
00000168 <main>:
168: fe010113 addi sp,sp,-32
16c: 00812e23 sw s0,28(sp)
170: 02010413 addi s0,sp,32
174: 10000797 auipc a5,0x10000
178: e8c78793 addi a5,a5,-372 # 10000000 <_data>
17c: 00600713 li a4,6
180: 00e7a023 sw a4,0(a5)
184: fe042423 sw zero,-24(s0)
188: fe042623 sw zero,-20(s0)
18c: 0200006f j 1ac <main+0x44>
190: fe842703 lw a4,-24(s0)
194: fec42783 lw a5,-20(s0)
198: 00f707b3 add a5,a4,a5
19c: fef42423 sw a5,-24(s0)
1a0: fec42783 lw a5,-20(s0)
1a4: 00178793 addi a5,a5,1
1a8: fef42623 sw a5,-20(s0)
1ac: fec42703 lw a4,-20(s0)
1b0: 06400793 li a5,100
1b4: fce7dee3 bge a5,a4,190 <main+0x28>
1b8: fe042623 sw zero,-20(s0)
1bc: 0200006f j 1dc <main+0x74>
1c0: fe842703 lw a4,-24(s0)
1c4: fec42783 lw a5,-20(s0)
1c8: 40f707b3 sub a5,a4,a5
1cc: fef42423 sw a5,-24(s0)
1d0: fec42783 lw a5,-20(s0)
1d4: 00178793 addi a5,a5,1
1d8: fef42623 sw a5,-20(s0)
1dc: fec42703 lw a4,-20(s0)
1e0: 03200793 li a5,50
1e4: fce7dee3 bge a5,a4,1c0 <main+0x58>
1e8: 10000797 auipc a5,0x10000
1ec: e1878793 addi a5,a5,-488 # 10000000 <_data>
1f0: 0007a783 lw a5,0(a5)
1f4: fe842703 lw a4,-24(s0)
1f8: 02f707b3 mul a5,a4,a5
1fc: fef42423 sw a5,-24(s0)
200: 10000797 auipc a5,0x10000
204: e0478793 addi a5,a5,-508 # 10000004 <div>
208: 0007a783 lw a5,0(a5)
20c: fe842703 lw a4,-24(s0)
210: 02f747b3 div a5,a4,a5
214: fef42423 sw a5,-24(s0)
218: fe842703 lw a4,-24(s0)
21c: 000027b7 lui a5,0x2
220: d7e78793 addi a5,a5,-642 # 1d7e <__stack_size+0x157e>
224: 00f71663 bne a4,a5,230 <main+0xc8>
228: 00100d93 li s11,1
22c: 0080006f j 234 <main+0xcc>
230: 00000d93 li s11,0
234: 00000793 li a5,0
238: 00078513 mv a0,a5
23c: 01c12403 lw s0,28(sp)
240: 02010113 addi sp,sp,32
244: 00008067 ret
00000248 <trap_handler>:
248: fe010113 addi sp,sp,-32
24c: 00112e23 sw ra,28(sp)
250: 00812c23 sw s0,24(sp)
254: 02010413 addi s0,sp,32
258: fea42623 sw a0,-20(s0)
25c: 00000097 auipc ra,0x0
260: 000000e7 jalr zero # 0 <_start>
264: 00000013 nop
268: 01c12083 lw ra,28(sp)
26c: 01812403 lw s0,24(sp)
270: 02010113 addi sp,sp,32
274: 00008067 ret
00000278 <_init>:
278: ff010113 addi sp,sp,-16
27c: 00812623 sw s0,12(sp)
280: 01010413 addi s0,sp,16
284: 00000797 auipc a5,0x0
288: de478793 addi a5,a5,-540 # 68 <trap_entry>
28c: 30579073 csrw mtvec,a5
290: 00000013 nop
294: 00c12403 lw s0,12(sp)
298: 01010113 addi sp,sp,16
29c: 00008067 ret
Disassembly of section .data:
10000000 <mul>:
10000000: 00000003 lb zero,0(zero) # 0 <_start>
10000004 <div>:
10000004: 00000003 lb zero,0(zero) # 0 <_start>
Disassembly of section .stack:
10001800 <_sp-0x800>:
...
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <trap_entry+0x48>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <trap_entry+0x54>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...

7
tests/example/spi_master/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
spi_master.bin
spi_master.dump
spi_master

Binary file not shown.

File diff suppressed because it is too large Load Diff

7
tests/example/timer_int/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
timer_int.bin
timer_int.dump
timer_int

Binary file not shown.

View File

@ -1,187 +0,0 @@
timer_int: file format elf32-littleriscv
Disassembly of section .init:
00000000 <_start>:
0: 10001197 auipc gp,0x10001
4: 80018193 addi gp,gp,-2048 # 10000800 <__global_pointer$>
8: 10002117 auipc sp,0x10002
c: ff810113 addi sp,sp,-8 # 10002000 <_sp>
10: 00000d13 li s10,0
14: 00000d93 li s11,0
18: 1f800513 li a0,504
1c: 10000597 auipc a1,0x10000
20: fe458593 addi a1,a1,-28 # 10000000 <_data>
24: 10000617 auipc a2,0x10000
28: fdc60613 addi a2,a2,-36 # 10000000 <_data>
2c: 00c5fc63 bgeu a1,a2,44 <_start+0x44>
30: 00052283 lw t0,0(a0)
34: 0055a023 sw t0,0(a1)
38: 00450513 addi a0,a0,4
3c: 00458593 addi a1,a1,4
40: fec5e8e3 bltu a1,a2,30 <_start+0x30>
44: 10000517 auipc a0,0x10000
48: fbc50513 addi a0,a0,-68 # 10000000 <_data>
4c: 80818593 addi a1,gp,-2040 # 10000008 <_end>
50: 00b57863 bgeu a0,a1,60 <_start+0x60>
54: 00052023 sw zero,0(a0)
58: 00450513 addi a0,a0,4
5c: feb56ce3 bltu a0,a1,54 <_start+0x54>
60: 188000ef jal ra,1e8 <_init>
64: 00c000ef jal ra,70 <main>
68: 00100d13 li s10,1
0000006c <loop>:
6c: 0000006f j 6c <loop>
Disassembly of section .text:
00000070 <main>:
70: 10000797 auipc a5,0x10000
74: f807a823 sw zero,-112(a5) # 10000000 <_data>
78: 200007b7 lui a5,0x20000
7c: 1f400713 li a4,500
80: 00e7a423 sw a4,8(a5) # 20000008 <_sp+0xfffe008>
84: 00700713 li a4,7
88: 00e7a023 sw a4,0(a5)
8c: 10000697 auipc a3,0x10000
90: f7468693 addi a3,a3,-140 # 10000000 <_data>
94: 00200793 li a5,2
98: 0006a703 lw a4,0(a3)
9c: fef71ee3 bne a4,a5,98 <main+0x28>
a0: 200007b7 lui a5,0x20000
a4: 0007a023 sw zero,0(a5) # 20000000 <_sp+0xfffe000>
a8: 10000797 auipc a5,0x10000
ac: f407ac23 sw zero,-168(a5) # 10000000 <_data>
b0: 00100d93 li s11,1
b4: 00000513 li a0,0
b8: 00008067 ret
000000bc <trap_entry>:
bc: f8010113 addi sp,sp,-128
c0: 00112223 sw ra,4(sp)
c4: 00212423 sw sp,8(sp)
c8: 00312623 sw gp,12(sp)
cc: 00412823 sw tp,16(sp)
d0: 00512a23 sw t0,20(sp)
d4: 00612c23 sw t1,24(sp)
d8: 00712e23 sw t2,28(sp)
dc: 02812023 sw s0,32(sp)
e0: 02912223 sw s1,36(sp)
e4: 02a12423 sw a0,40(sp)
e8: 02b12623 sw a1,44(sp)
ec: 02c12823 sw a2,48(sp)
f0: 02d12a23 sw a3,52(sp)
f4: 02e12c23 sw a4,56(sp)
f8: 02f12e23 sw a5,60(sp)
fc: 05012023 sw a6,64(sp)
100: 05112223 sw a7,68(sp)
104: 05212423 sw s2,72(sp)
108: 05312623 sw s3,76(sp)
10c: 05412823 sw s4,80(sp)
110: 05512a23 sw s5,84(sp)
114: 05612c23 sw s6,88(sp)
118: 05712e23 sw s7,92(sp)
11c: 07812023 sw s8,96(sp)
120: 07912223 sw s9,100(sp)
124: 07c12823 sw t3,112(sp)
128: 07d12a23 sw t4,116(sp)
12c: 07e12c23 sw t5,120(sp)
130: 07f12e23 sw t6,124(sp)
134: 34202573 csrr a0,mcause
138: 0ac000ef jal ra,1e4 <trap_handler>
13c: 00412083 lw ra,4(sp)
140: 00812103 lw sp,8(sp)
144: 00c12183 lw gp,12(sp)
148: 01012203 lw tp,16(sp)
14c: 01412283 lw t0,20(sp)
150: 01812303 lw t1,24(sp)
154: 01c12383 lw t2,28(sp)
158: 02012403 lw s0,32(sp)
15c: 02412483 lw s1,36(sp)
160: 02812503 lw a0,40(sp)
164: 02c12583 lw a1,44(sp)
168: 03012603 lw a2,48(sp)
16c: 03412683 lw a3,52(sp)
170: 03812703 lw a4,56(sp)
174: 03c12783 lw a5,60(sp)
178: 04012803 lw a6,64(sp)
17c: 04412883 lw a7,68(sp)
180: 04812903 lw s2,72(sp)
184: 04c12983 lw s3,76(sp)
188: 05012a03 lw s4,80(sp)
18c: 05412a83 lw s5,84(sp)
190: 05812b03 lw s6,88(sp)
194: 05c12b83 lw s7,92(sp)
198: 06012c03 lw s8,96(sp)
19c: 06412c83 lw s9,100(sp)
1a0: 07012e03 lw t3,112(sp)
1a4: 07412e83 lw t4,116(sp)
1a8: 07812f03 lw t5,120(sp)
1ac: 07c12f83 lw t6,124(sp)
1b0: 08010113 addi sp,sp,128
1b4: 30200073 mret
1b8: 0000006f j 1b8 <trap_entry+0xfc>
000001bc <timer0_irq_handler>:
1bc: 20000737 lui a4,0x20000
1c0: 00072783 lw a5,0(a4) # 20000000 <_sp+0xfffe000>
1c4: 0057e793 ori a5,a5,5
1c8: 00f72023 sw a5,0(a4)
1cc: 10000717 auipc a4,0x10000
1d0: e3470713 addi a4,a4,-460 # 10000000 <_data>
1d4: 00072783 lw a5,0(a4)
1d8: 00178793 addi a5,a5,1
1dc: 00f72023 sw a5,0(a4)
1e0: 00008067 ret
000001e4 <trap_handler>:
1e4: fd9ff06f j 1bc <timer0_irq_handler>
000001e8 <_init>:
1e8: 00000797 auipc a5,0x0
1ec: ed478793 addi a5,a5,-300 # bc <trap_entry>
1f0: 30579073 csrw mtvec,a5
1f4: 00008067 ret
Disassembly of section .bss:
10000000 <__bss_start>:
10000000: 0000 unimp
...
Disassembly of section .stack:
10001800 <_sp-0x800>:
...
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <main+0x40>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <trap_entry>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...

7
tests/example/uart_rx/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
uart_rx.bin
uart_rx.dump
uart_rx

Binary file not shown.

Binary file not shown.

View File

@ -1,681 +0,0 @@
uart_rx: file format elf32-littleriscv
Disassembly of section .init:
00000000 <_start>:
0: 10001197 auipc gp,0x10001
4: 86018193 addi gp,gp,-1952 # 10000860 <__global_pointer$>
8: 10004117 auipc sp,0x10004
c: ff810113 addi sp,sp,-8 # 10004000 <__freertos_irq_stack_top>
10: 00001517 auipc a0,0x1
14: 89050513 addi a0,a0,-1904 # 8a0 <_data_lma>
18: 10000597 auipc a1,0x10000
1c: fe858593 addi a1,a1,-24 # 10000000 <_data>
20: 10000617 auipc a2,0x10000
24: 04060613 addi a2,a2,64 # 10000060 <__bss_start>
28: 00c5fc63 bgeu a1,a2,40 <_start+0x40>
2c: 00052283 lw t0,0(a0)
30: 0055a023 sw t0,0(a1)
34: 00450513 addi a0,a0,4
38: 00458593 addi a1,a1,4
3c: fec5e8e3 bltu a1,a2,2c <_start+0x2c>
40: 10000517 auipc a0,0x10000
44: 02050513 addi a0,a0,32 # 10000060 <__bss_start>
48: 80818593 addi a1,gp,-2040 # 10000068 <_end>
4c: 00b57863 bgeu a0,a1,5c <_start+0x5c>
50: 00052023 sw zero,0(a0)
54: 00450513 addi a0,a0,4
58: feb56ce3 bltu a0,a1,50 <_start+0x50>
5c: 17c000ef jal ra,1d8 <_init>
60: 118000ef jal ra,178 <main>
00000064 <loop>:
64: 0000006f j 64 <loop>
Disassembly of section .text:
00000068 <trap_entry>:
68: f8010113 addi sp,sp,-128
6c: 00112223 sw ra,4(sp)
70: 00212423 sw sp,8(sp)
74: 00312623 sw gp,12(sp)
78: 00412823 sw tp,16(sp)
7c: 00512a23 sw t0,20(sp)
80: 00612c23 sw t1,24(sp)
84: 00712e23 sw t2,28(sp)
88: 02812023 sw s0,32(sp)
8c: 02912223 sw s1,36(sp)
90: 02a12423 sw a0,40(sp)
94: 02b12623 sw a1,44(sp)
98: 02c12823 sw a2,48(sp)
9c: 02d12a23 sw a3,52(sp)
a0: 02e12c23 sw a4,56(sp)
a4: 02f12e23 sw a5,60(sp)
a8: 05012023 sw a6,64(sp)
ac: 05112223 sw a7,68(sp)
b0: 05212423 sw s2,72(sp)
b4: 05312623 sw s3,76(sp)
b8: 05412823 sw s4,80(sp)
bc: 05512a23 sw s5,84(sp)
c0: 05612c23 sw s6,88(sp)
c4: 05712e23 sw s7,92(sp)
c8: 07812023 sw s8,96(sp)
cc: 07912223 sw s9,100(sp)
d0: 07a12423 sw s10,104(sp)
d4: 07b12623 sw s11,108(sp)
d8: 07c12823 sw t3,112(sp)
dc: 07d12a23 sw t4,116(sp)
e0: 07e12c23 sw t5,120(sp)
e4: 07f12e23 sw t6,124(sp)
e8: 34202573 csrr a0,mcause
ec: 0bc000ef jal ra,1a8 <trap_handler>
f0: 00412083 lw ra,4(sp)
f4: 00812103 lw sp,8(sp)
f8: 00c12183 lw gp,12(sp)
fc: 01012203 lw tp,16(sp)
100: 01412283 lw t0,20(sp)
104: 01812303 lw t1,24(sp)
108: 01c12383 lw t2,28(sp)
10c: 02012403 lw s0,32(sp)
110: 02412483 lw s1,36(sp)
114: 02812503 lw a0,40(sp)
118: 02c12583 lw a1,44(sp)
11c: 03012603 lw a2,48(sp)
120: 03412683 lw a3,52(sp)
124: 03812703 lw a4,56(sp)
128: 03c12783 lw a5,60(sp)
12c: 04012803 lw a6,64(sp)
130: 04412883 lw a7,68(sp)
134: 04812903 lw s2,72(sp)
138: 04c12983 lw s3,76(sp)
13c: 05012a03 lw s4,80(sp)
140: 05412a83 lw s5,84(sp)
144: 05812b03 lw s6,88(sp)
148: 05c12b83 lw s7,92(sp)
14c: 06012c03 lw s8,96(sp)
150: 06412c83 lw s9,100(sp)
154: 06812d03 lw s10,104(sp)
158: 06c12d83 lw s11,108(sp)
15c: 07012e03 lw t3,112(sp)
160: 07412e83 lw t4,116(sp)
164: 07812f03 lw t5,120(sp)
168: 07c12f83 lw t6,124(sp)
16c: 08010113 addi sp,sp,128
170: 30200073 mret
174: 0000006f j 174 <trap_entry+0x10c>
00000178 <main>:
178: ff010113 addi sp,sp,-16
17c: 00112623 sw ra,12(sp)
180: 00812423 sw s0,8(sp)
184: 01010413 addi s0,sp,16
188: 6e0000ef jal ra,868 <uart_init>
18c: 67c000ef jal ra,808 <uart_getc>
190: 00050793 mv a5,a0
194: 00078593 mv a1,a5
198: 100007b7 lui a5,0x10000
19c: 00078513 mv a0,a5
1a0: 5bc000ef jal ra,75c <xprintf>
1a4: fe9ff06f j 18c <main+0x14>
000001a8 <trap_handler>:
1a8: fe010113 addi sp,sp,-32
1ac: 00112e23 sw ra,28(sp)
1b0: 00812c23 sw s0,24(sp)
1b4: 02010413 addi s0,sp,32
1b8: fea42623 sw a0,-20(s0)
1bc: 00000097 auipc ra,0x0
1c0: 000000e7 jalr zero # 0 <_start>
1c4: 00000013 nop
1c8: 01c12083 lw ra,28(sp)
1cc: 01812403 lw s0,24(sp)
1d0: 02010113 addi sp,sp,32
1d4: 00008067 ret
000001d8 <_init>:
1d8: ff010113 addi sp,sp,-16
1dc: 00812623 sw s0,12(sp)
1e0: 01010413 addi s0,sp,16
1e4: 000007b7 lui a5,0x0
1e8: 06878793 addi a5,a5,104 # 68 <trap_entry>
1ec: 30579073 csrw mtvec,a5
1f0: 000027b7 lui a5,0x2
1f4: 88878793 addi a5,a5,-1912 # 1888 <_data_lma+0xfe8>
1f8: 30079073 csrw mstatus,a5
1fc: 00000013 nop
200: 00c12403 lw s0,12(sp)
204: 01010113 addi sp,sp,16
208: 00008067 ret
0000020c <xputc>:
20c: fe010113 addi sp,sp,-32
210: 00112e23 sw ra,28(sp)
214: 00812c23 sw s0,24(sp)
218: 02010413 addi s0,sp,32
21c: 00050793 mv a5,a0
220: fef407a3 sb a5,-17(s0)
224: 100007b7 lui a5,0x10000
228: 0607a783 lw a5,96(a5) # 10000060 <__bss_start>
22c: 02078263 beqz a5,250 <xputc+0x44>
230: 100007b7 lui a5,0x10000
234: 0607a783 lw a5,96(a5) # 10000060 <__bss_start>
238: 00178693 addi a3,a5,1
23c: 10000737 lui a4,0x10000
240: 06d72023 sw a3,96(a4) # 10000060 <__bss_start>
244: fef44703 lbu a4,-17(s0)
248: 00e78023 sb a4,0(a5)
24c: 0240006f j 270 <xputc+0x64>
250: 100007b7 lui a5,0x10000
254: 0647a783 lw a5,100(a5) # 10000064 <xfunc_out>
258: 00078c63 beqz a5,270 <xputc+0x64>
25c: 100007b7 lui a5,0x10000
260: 0647a703 lw a4,100(a5) # 10000064 <xfunc_out>
264: fef44783 lbu a5,-17(s0)
268: 00078513 mv a0,a5
26c: 000700e7 jalr a4
270: 01c12083 lw ra,28(sp)
274: 01812403 lw s0,24(sp)
278: 02010113 addi sp,sp,32
27c: 00008067 ret
00000280 <xputs>:
280: fe010113 addi sp,sp,-32
284: 00112e23 sw ra,28(sp)
288: 00812c23 sw s0,24(sp)
28c: 02010413 addi s0,sp,32
290: fea42623 sw a0,-20(s0)
294: 01c0006f j 2b0 <xputs+0x30>
298: fec42783 lw a5,-20(s0)
29c: 00178713 addi a4,a5,1
2a0: fee42623 sw a4,-20(s0)
2a4: 0007c783 lbu a5,0(a5)
2a8: 00078513 mv a0,a5
2ac: f61ff0ef jal ra,20c <xputc>
2b0: fec42783 lw a5,-20(s0)
2b4: 0007c783 lbu a5,0(a5)
2b8: fe0790e3 bnez a5,298 <xputs+0x18>
2bc: 00000013 nop
2c0: 01c12083 lw ra,28(sp)
2c4: 01812403 lw s0,24(sp)
2c8: 02010113 addi sp,sp,32
2cc: 00008067 ret
000002d0 <xvprintf>:
2d0: fb010113 addi sp,sp,-80
2d4: 04112623 sw ra,76(sp)
2d8: 04812423 sw s0,72(sp)
2dc: 05010413 addi s0,sp,80
2e0: faa42e23 sw a0,-68(s0)
2e4: fab42c23 sw a1,-72(s0)
2e8: fbc42783 lw a5,-68(s0)
2ec: 00178713 addi a4,a5,1
2f0: fae42e23 sw a4,-68(s0)
2f4: 0007c783 lbu a5,0(a5)
2f8: fcf40ba3 sb a5,-41(s0)
2fc: fd744783 lbu a5,-41(s0)
300: 42078e63 beqz a5,73c <xvprintf+0x46c>
304: fd744703 lbu a4,-41(s0)
308: 02500793 li a5,37
30c: 00f70a63 beq a4,a5,320 <xvprintf+0x50>
310: fd744783 lbu a5,-41(s0)
314: 00078513 mv a0,a5
318: ef5ff0ef jal ra,20c <xputc>
31c: 41c0006f j 738 <xvprintf+0x468>
320: fc042e23 sw zero,-36(s0)
324: fbc42783 lw a5,-68(s0)
328: 00178713 addi a4,a5,1
32c: fae42e23 sw a4,-68(s0)
330: 0007c783 lbu a5,0(a5)
334: fcf40ba3 sb a5,-41(s0)
338: fd744703 lbu a4,-41(s0)
33c: 03000793 li a5,48
340: 02f71263 bne a4,a5,364 <xvprintf+0x94>
344: 00100793 li a5,1
348: fcf42e23 sw a5,-36(s0)
34c: fbc42783 lw a5,-68(s0)
350: 00178713 addi a4,a5,1
354: fae42e23 sw a4,-68(s0)
358: 0007c783 lbu a5,0(a5)
35c: fcf40ba3 sb a5,-41(s0)
360: 02c0006f j 38c <xvprintf+0xbc>
364: fd744703 lbu a4,-41(s0)
368: 02d00793 li a5,45
36c: 02f71063 bne a4,a5,38c <xvprintf+0xbc>
370: 00200793 li a5,2
374: fcf42e23 sw a5,-36(s0)
378: fbc42783 lw a5,-68(s0)
37c: 00178713 addi a4,a5,1
380: fae42e23 sw a4,-68(s0)
384: 0007c783 lbu a5,0(a5)
388: fcf40ba3 sb a5,-41(s0)
38c: fe042023 sw zero,-32(s0)
390: 0400006f j 3d0 <xvprintf+0x100>
394: fe042703 lw a4,-32(s0)
398: 00070793 mv a5,a4
39c: 00279793 slli a5,a5,0x2
3a0: 00e787b3 add a5,a5,a4
3a4: 00179793 slli a5,a5,0x1
3a8: 00078713 mv a4,a5
3ac: fd744783 lbu a5,-41(s0)
3b0: 00f707b3 add a5,a4,a5
3b4: fd078793 addi a5,a5,-48
3b8: fef42023 sw a5,-32(s0)
3bc: fbc42783 lw a5,-68(s0)
3c0: 00178713 addi a4,a5,1
3c4: fae42e23 sw a4,-68(s0)
3c8: 0007c783 lbu a5,0(a5)
3cc: fcf40ba3 sb a5,-41(s0)
3d0: fd744703 lbu a4,-41(s0)
3d4: 02f00793 li a5,47
3d8: 00e7f863 bgeu a5,a4,3e8 <xvprintf+0x118>
3dc: fd744703 lbu a4,-41(s0)
3e0: 03900793 li a5,57
3e4: fae7f8e3 bgeu a5,a4,394 <xvprintf+0xc4>
3e8: fd744703 lbu a4,-41(s0)
3ec: 06c00793 li a5,108
3f0: 00f70863 beq a4,a5,400 <xvprintf+0x130>
3f4: fd744703 lbu a4,-41(s0)
3f8: 04c00793 li a5,76
3fc: 02f71263 bne a4,a5,420 <xvprintf+0x150>
400: fdc42783 lw a5,-36(s0)
404: 0047e793 ori a5,a5,4
408: fcf42e23 sw a5,-36(s0)
40c: fbc42783 lw a5,-68(s0)
410: 00178713 addi a4,a5,1
414: fae42e23 sw a4,-68(s0)
418: 0007c783 lbu a5,0(a5)
41c: fcf40ba3 sb a5,-41(s0)
420: fd744783 lbu a5,-41(s0)
424: 32078063 beqz a5,744 <xvprintf+0x474>
428: fd744783 lbu a5,-41(s0)
42c: fcf40b23 sb a5,-42(s0)
430: fd644703 lbu a4,-42(s0)
434: 06000793 li a5,96
438: 00e7f863 bgeu a5,a4,448 <xvprintf+0x178>
43c: fd644783 lbu a5,-42(s0)
440: fe078793 addi a5,a5,-32
444: fcf40b23 sb a5,-42(s0)
448: fd644783 lbu a5,-42(s0)
44c: fbe78793 addi a5,a5,-66
450: 01600713 li a4,22
454: 10f76063 bltu a4,a5,554 <xvprintf+0x284>
458: 00279713 slli a4,a5,0x2
45c: 100007b7 lui a5,0x10000
460: 00478793 addi a5,a5,4 # 10000004 <_data+0x4>
464: 00f707b3 add a5,a4,a5
468: 0007a783 lw a5,0(a5)
46c: 00078067 jr a5
470: fb842783 lw a5,-72(s0)
474: 00478713 addi a4,a5,4
478: fae42c23 sw a4,-72(s0)
47c: 0007a783 lw a5,0(a5)
480: fcf42823 sw a5,-48(s0)
484: fe042223 sw zero,-28(s0)
488: 0100006f j 498 <xvprintf+0x1c8>
48c: fe442783 lw a5,-28(s0)
490: 00178793 addi a5,a5,1
494: fef42223 sw a5,-28(s0)
498: fd042703 lw a4,-48(s0)
49c: fe442783 lw a5,-28(s0)
4a0: 00f707b3 add a5,a4,a5
4a4: 0007c783 lbu a5,0(a5)
4a8: fe0792e3 bnez a5,48c <xvprintf+0x1bc>
4ac: 00c0006f j 4b8 <xvprintf+0x1e8>
4b0: 02000513 li a0,32
4b4: d59ff0ef jal ra,20c <xputc>
4b8: fdc42783 lw a5,-36(s0)
4bc: 0027f793 andi a5,a5,2
4c0: 00079c63 bnez a5,4d8 <xvprintf+0x208>
4c4: fe442783 lw a5,-28(s0)
4c8: 00178713 addi a4,a5,1
4cc: fee42223 sw a4,-28(s0)
4d0: fe042703 lw a4,-32(s0)
4d4: fce7eee3 bltu a5,a4,4b0 <xvprintf+0x1e0>
4d8: fd042503 lw a0,-48(s0)
4dc: da5ff0ef jal ra,280 <xputs>
4e0: 00c0006f j 4ec <xvprintf+0x21c>
4e4: 02000513 li a0,32
4e8: d25ff0ef jal ra,20c <xputc>
4ec: fe442783 lw a5,-28(s0)
4f0: 00178713 addi a4,a5,1
4f4: fee42223 sw a4,-28(s0)
4f8: fe042703 lw a4,-32(s0)
4fc: fee7e4e3 bltu a5,a4,4e4 <xvprintf+0x214>
500: 2380006f j 738 <xvprintf+0x468>
504: fb842783 lw a5,-72(s0)
508: 00478713 addi a4,a5,4
50c: fae42c23 sw a4,-72(s0)
510: 0007a783 lw a5,0(a5)
514: 0ff7f793 andi a5,a5,255
518: 00078513 mv a0,a5
51c: cf1ff0ef jal ra,20c <xputc>
520: 2180006f j 738 <xvprintf+0x468>
524: 00200793 li a5,2
528: fef42623 sw a5,-20(s0)
52c: 0380006f j 564 <xvprintf+0x294>
530: 00800793 li a5,8
534: fef42623 sw a5,-20(s0)
538: 02c0006f j 564 <xvprintf+0x294>
53c: 00a00793 li a5,10
540: fef42623 sw a5,-20(s0)
544: 0200006f j 564 <xvprintf+0x294>
548: 01000793 li a5,16
54c: fef42623 sw a5,-20(s0)
550: 0140006f j 564 <xvprintf+0x294>
554: fd744783 lbu a5,-41(s0)
558: 00078513 mv a0,a5
55c: cb1ff0ef jal ra,20c <xputc>
560: 1d80006f j 738 <xvprintf+0x468>
564: fdc42783 lw a5,-36(s0)
568: 0047f793 andi a5,a5,4
56c: 00078c63 beqz a5,584 <xvprintf+0x2b4>
570: fb842783 lw a5,-72(s0)
574: 00478713 addi a4,a5,4
578: fae42c23 sw a4,-72(s0)
57c: 0007a783 lw a5,0(a5)
580: 0340006f j 5b4 <xvprintf+0x2e4>
584: fd644703 lbu a4,-42(s0)
588: 04400793 li a5,68
58c: 00f71c63 bne a4,a5,5a4 <xvprintf+0x2d4>
590: fb842783 lw a5,-72(s0)
594: 00478713 addi a4,a5,4
598: fae42c23 sw a4,-72(s0)
59c: 0007a783 lw a5,0(a5)
5a0: 0140006f j 5b4 <xvprintf+0x2e4>
5a4: fb842783 lw a5,-72(s0)
5a8: 00478713 addi a4,a5,4
5ac: fae42c23 sw a4,-72(s0)
5b0: 0007a783 lw a5,0(a5)
5b4: fcf42c23 sw a5,-40(s0)
5b8: fd644703 lbu a4,-42(s0)
5bc: 04400793 li a5,68
5c0: 02f71263 bne a4,a5,5e4 <xvprintf+0x314>
5c4: fd842783 lw a5,-40(s0)
5c8: 0007de63 bgez a5,5e4 <xvprintf+0x314>
5cc: fd842783 lw a5,-40(s0)
5d0: 40f007b3 neg a5,a5
5d4: fcf42c23 sw a5,-40(s0)
5d8: fdc42783 lw a5,-36(s0)
5dc: 0087e793 ori a5,a5,8
5e0: fcf42e23 sw a5,-36(s0)
5e4: fe042423 sw zero,-24(s0)
5e8: fd842703 lw a4,-40(s0)
5ec: fec42783 lw a5,-20(s0)
5f0: 02f777b3 remu a5,a4,a5
5f4: fcf40b23 sb a5,-42(s0)
5f8: fd842703 lw a4,-40(s0)
5fc: fec42783 lw a5,-20(s0)
600: 02f757b3 divu a5,a4,a5
604: fcf42c23 sw a5,-40(s0)
608: fd644703 lbu a4,-42(s0)
60c: 00900793 li a5,9
610: 02e7f463 bgeu a5,a4,638 <xvprintf+0x368>
614: fd744703 lbu a4,-41(s0)
618: 07800793 li a5,120
61c: 00f71663 bne a4,a5,628 <xvprintf+0x358>
620: 02700793 li a5,39
624: 0080006f j 62c <xvprintf+0x35c>
628: 00700793 li a5,7
62c: fd644703 lbu a4,-42(s0)
630: 00e787b3 add a5,a5,a4
634: fcf40b23 sb a5,-42(s0)
638: fe842783 lw a5,-24(s0)
63c: 00178713 addi a4,a5,1
640: fee42423 sw a4,-24(s0)
644: fd644703 lbu a4,-42(s0)
648: 03070713 addi a4,a4,48
64c: 0ff77713 andi a4,a4,255
650: ff040693 addi a3,s0,-16
654: 00f687b3 add a5,a3,a5
658: fce78823 sb a4,-48(a5)
65c: fd842783 lw a5,-40(s0)
660: 00078863 beqz a5,670 <xvprintf+0x3a0>
664: fe842703 lw a4,-24(s0)
668: 00f00793 li a5,15
66c: f6e7fee3 bgeu a5,a4,5e8 <xvprintf+0x318>
670: fdc42783 lw a5,-36(s0)
674: 0087f793 andi a5,a5,8
678: 02078063 beqz a5,698 <xvprintf+0x3c8>
67c: fe842783 lw a5,-24(s0)
680: 00178713 addi a4,a5,1
684: fee42423 sw a4,-24(s0)
688: ff040713 addi a4,s0,-16
68c: 00f707b3 add a5,a4,a5
690: 02d00713 li a4,45
694: fce78823 sb a4,-48(a5)
698: fe842783 lw a5,-24(s0)
69c: fef42223 sw a5,-28(s0)
6a0: fdc42783 lw a5,-36(s0)
6a4: 0017f793 andi a5,a5,1
6a8: 00078663 beqz a5,6b4 <xvprintf+0x3e4>
6ac: 03000793 li a5,48
6b0: 0080006f j 6b8 <xvprintf+0x3e8>
6b4: 02000793 li a5,32
6b8: fcf40b23 sb a5,-42(s0)
6bc: 0100006f j 6cc <xvprintf+0x3fc>
6c0: fd644783 lbu a5,-42(s0)
6c4: 00078513 mv a0,a5
6c8: b45ff0ef jal ra,20c <xputc>
6cc: fdc42783 lw a5,-36(s0)
6d0: 0027f793 andi a5,a5,2
6d4: 00079c63 bnez a5,6ec <xvprintf+0x41c>
6d8: fe442783 lw a5,-28(s0)
6dc: 00178713 addi a4,a5,1
6e0: fee42223 sw a4,-28(s0)
6e4: fe042703 lw a4,-32(s0)
6e8: fce7ece3 bltu a5,a4,6c0 <xvprintf+0x3f0>
6ec: fe842783 lw a5,-24(s0)
6f0: fff78793 addi a5,a5,-1
6f4: fef42423 sw a5,-24(s0)
6f8: fe842783 lw a5,-24(s0)
6fc: ff040713 addi a4,s0,-16
700: 00f707b3 add a5,a4,a5
704: fd07c783 lbu a5,-48(a5)
708: 00078513 mv a0,a5
70c: b01ff0ef jal ra,20c <xputc>
710: fe842783 lw a5,-24(s0)
714: fc079ce3 bnez a5,6ec <xvprintf+0x41c>
718: 00c0006f j 724 <xvprintf+0x454>
71c: 02000513 li a0,32
720: aedff0ef jal ra,20c <xputc>
724: fe442783 lw a5,-28(s0)
728: 00178713 addi a4,a5,1
72c: fee42223 sw a4,-28(s0)
730: fe042703 lw a4,-32(s0)
734: fee7e4e3 bltu a5,a4,71c <xvprintf+0x44c>
738: bb1ff06f j 2e8 <xvprintf+0x18>
73c: 00000013 nop
740: 0080006f j 748 <xvprintf+0x478>
744: 00000013 nop
748: 00000013 nop
74c: 04c12083 lw ra,76(sp)
750: 04812403 lw s0,72(sp)
754: 05010113 addi sp,sp,80
758: 00008067 ret
0000075c <xprintf>:
75c: fb010113 addi sp,sp,-80
760: 02112623 sw ra,44(sp)
764: 02812423 sw s0,40(sp)
768: 03010413 addi s0,sp,48
76c: fca42e23 sw a0,-36(s0)
770: 00b42223 sw a1,4(s0)
774: 00c42423 sw a2,8(s0)
778: 00d42623 sw a3,12(s0)
77c: 00e42823 sw a4,16(s0)
780: 00f42a23 sw a5,20(s0)
784: 01042c23 sw a6,24(s0)
788: 01142e23 sw a7,28(s0)
78c: 02040793 addi a5,s0,32
790: fe478793 addi a5,a5,-28
794: fef42623 sw a5,-20(s0)
798: fec42783 lw a5,-20(s0)
79c: 00078593 mv a1,a5
7a0: fdc42503 lw a0,-36(s0)
7a4: b2dff0ef jal ra,2d0 <xvprintf>
7a8: 00000013 nop
7ac: 02c12083 lw ra,44(sp)
7b0: 02812403 lw s0,40(sp)
7b4: 05010113 addi sp,sp,80
7b8: 00008067 ret
000007bc <uart_putc>:
7bc: fe010113 addi sp,sp,-32
7c0: 00812e23 sw s0,28(sp)
7c4: 02010413 addi s0,sp,32
7c8: 00050793 mv a5,a0
7cc: fef407a3 sb a5,-17(s0)
7d0: 00000013 nop
7d4: 300007b7 lui a5,0x30000
7d8: 00478793 addi a5,a5,4 # 30000004 <__freertos_irq_stack_top+0x1fffc004>
7dc: 0007a783 lw a5,0(a5)
7e0: 0017f793 andi a5,a5,1
7e4: fe0798e3 bnez a5,7d4 <uart_putc+0x18>
7e8: 300007b7 lui a5,0x30000
7ec: 00c78793 addi a5,a5,12 # 3000000c <__freertos_irq_stack_top+0x1fffc00c>
7f0: fef44703 lbu a4,-17(s0)
7f4: 00e7a023 sw a4,0(a5)
7f8: 00000013 nop
7fc: 01c12403 lw s0,28(sp)
800: 02010113 addi sp,sp,32
804: 00008067 ret
00000808 <uart_getc>:
808: ff010113 addi sp,sp,-16
80c: 00812623 sw s0,12(sp)
810: 01010413 addi s0,sp,16
814: 300007b7 lui a5,0x30000
818: 00478793 addi a5,a5,4 # 30000004 <__freertos_irq_stack_top+0x1fffc004>
81c: 0007a703 lw a4,0(a5)
820: 300007b7 lui a5,0x30000
824: 00478793 addi a5,a5,4 # 30000004 <__freertos_irq_stack_top+0x1fffc004>
828: ffd77713 andi a4,a4,-3
82c: 00e7a023 sw a4,0(a5)
830: 00000013 nop
834: 300007b7 lui a5,0x30000
838: 00478793 addi a5,a5,4 # 30000004 <__freertos_irq_stack_top+0x1fffc004>
83c: 0007a783 lw a5,0(a5)
840: 0027f793 andi a5,a5,2
844: fe0788e3 beqz a5,834 <uart_getc+0x2c>
848: 300007b7 lui a5,0x30000
84c: 01078793 addi a5,a5,16 # 30000010 <__freertos_irq_stack_top+0x1fffc010>
850: 0007a783 lw a5,0(a5)
854: 0ff7f793 andi a5,a5,255
858: 00078513 mv a0,a5
85c: 00c12403 lw s0,12(sp)
860: 01010113 addi sp,sp,16
864: 00008067 ret
00000868 <uart_init>:
868: ff010113 addi sp,sp,-16
86c: 00812623 sw s0,12(sp)
870: 01010413 addi s0,sp,16
874: 300007b7 lui a5,0x30000
878: 00300713 li a4,3
87c: 00e7a023 sw a4,0(a5) # 30000000 <__freertos_irq_stack_top+0x1fffc000>
880: 100007b7 lui a5,0x10000
884: 00000737 lui a4,0x0
888: 7bc70713 addi a4,a4,1980 # 7bc <uart_putc>
88c: 06e7a223 sw a4,100(a5) # 10000064 <xfunc_out>
890: 00000013 nop
894: 00c12403 lw s0,12(sp)
898: 01010113 addi sp,sp,16
89c: 00008067 ret
Disassembly of section .data:
10000000 <__global_pointer$-0x860>:
10000000: 6325 lui t1,0x9
10000002: 0000 unimp
10000004: 0524 addi s1,sp,648
10000006: 0000 unimp
10000008: 0504 addi s1,sp,640
1000000a: 0000 unimp
1000000c: 053c addi a5,sp,648
1000000e: 0000 unimp
10000010: 0554 addi a3,sp,644
10000012: 0000 unimp
10000014: 0554 addi a3,sp,644
10000016: 0000 unimp
10000018: 0554 addi a3,sp,644
1000001a: 0000 unimp
1000001c: 0554 addi a3,sp,644
1000001e: 0000 unimp
10000020: 0554 addi a3,sp,644
10000022: 0000 unimp
10000024: 0554 addi a3,sp,644
10000026: 0000 unimp
10000028: 0554 addi a3,sp,644
1000002a: 0000 unimp
1000002c: 0554 addi a3,sp,644
1000002e: 0000 unimp
10000030: 0554 addi a3,sp,644
10000032: 0000 unimp
10000034: 0554 addi a3,sp,644
10000036: 0000 unimp
10000038: 0530 addi a2,sp,648
1000003a: 0000 unimp
1000003c: 0554 addi a3,sp,644
1000003e: 0000 unimp
10000040: 0554 addi a3,sp,644
10000042: 0000 unimp
10000044: 0554 addi a3,sp,644
10000046: 0000 unimp
10000048: 0470 addi a2,sp,524
1000004a: 0000 unimp
1000004c: 0554 addi a3,sp,644
1000004e: 0000 unimp
10000050: 053c addi a5,sp,648
10000052: 0000 unimp
10000054: 0554 addi a3,sp,644
10000056: 0000 unimp
10000058: 0554 addi a3,sp,644
1000005a: 0000 unimp
1000005c: 0548 addi a0,sp,644
...
Disassembly of section .bss:
10000060 <__bss_start>:
10000060: 0000 unimp
...
10000064 <xfunc_out>:
10000064: 0000 unimp
...
Disassembly of section .stack:
10002000 <__freertos_irq_stack_top-0x2000>:
...
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <trap_entry+0x48>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <trap_entry+0x54>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...

7
tests/example/uart_tx/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
uart_tx.bin
uart_tx.dump
uart_tx

Binary file not shown.

Binary file not shown.

View File

@ -1,665 +0,0 @@
uart_tx: file format elf32-littleriscv
Disassembly of section .init:
00000000 <_start>:
0: 10001197 auipc gp,0x10001
4: 87018193 addi gp,gp,-1936 # 10000870 <__global_pointer$>
8: 10003117 auipc sp,0x10003
c: ff810113 addi sp,sp,-8 # 10003000 <_sp>
10: 00001517 auipc a0,0x1
14: 83c50513 addi a0,a0,-1988 # 84c <_data_lma>
18: 10000597 auipc a1,0x10000
1c: fe858593 addi a1,a1,-24 # 10000000 <_data>
20: 10000617 auipc a2,0x10000
24: 05060613 addi a2,a2,80 # 10000070 <__bss_start>
28: 00c5fc63 bgeu a1,a2,40 <_start+0x40>
2c: 00052283 lw t0,0(a0)
30: 0055a023 sw t0,0(a1)
34: 00450513 addi a0,a0,4
38: 00458593 addi a1,a1,4
3c: fec5e8e3 bltu a1,a2,2c <_start+0x2c>
40: 10000517 auipc a0,0x10000
44: 03050513 addi a0,a0,48 # 10000070 <__bss_start>
48: 80818593 addi a1,gp,-2040 # 10000078 <_end>
4c: 00b57863 bgeu a0,a1,5c <_start+0x5c>
50: 00052023 sw zero,0(a0)
54: 00450513 addi a0,a0,4
58: feb56ce3 bltu a0,a1,50 <_start+0x50>
5c: 170000ef jal ra,1cc <_init>
60: 118000ef jal ra,178 <main>
00000064 <loop>:
64: 0000006f j 64 <loop>
Disassembly of section .text:
00000068 <trap_entry>:
68: f8010113 addi sp,sp,-128
6c: 00112223 sw ra,4(sp)
70: 00212423 sw sp,8(sp)
74: 00312623 sw gp,12(sp)
78: 00412823 sw tp,16(sp)
7c: 00512a23 sw t0,20(sp)
80: 00612c23 sw t1,24(sp)
84: 00712e23 sw t2,28(sp)
88: 02812023 sw s0,32(sp)
8c: 02912223 sw s1,36(sp)
90: 02a12423 sw a0,40(sp)
94: 02b12623 sw a1,44(sp)
98: 02c12823 sw a2,48(sp)
9c: 02d12a23 sw a3,52(sp)
a0: 02e12c23 sw a4,56(sp)
a4: 02f12e23 sw a5,60(sp)
a8: 05012023 sw a6,64(sp)
ac: 05112223 sw a7,68(sp)
b0: 05212423 sw s2,72(sp)
b4: 05312623 sw s3,76(sp)
b8: 05412823 sw s4,80(sp)
bc: 05512a23 sw s5,84(sp)
c0: 05612c23 sw s6,88(sp)
c4: 05712e23 sw s7,92(sp)
c8: 07812023 sw s8,96(sp)
cc: 07912223 sw s9,100(sp)
d0: 07a12423 sw s10,104(sp)
d4: 07b12623 sw s11,108(sp)
d8: 07c12823 sw t3,112(sp)
dc: 07d12a23 sw t4,116(sp)
e0: 07e12c23 sw t5,120(sp)
e4: 07f12e23 sw t6,124(sp)
e8: 34202573 csrr a0,mcause
ec: 0b0000ef jal ra,19c <trap_handler>
f0: 00412083 lw ra,4(sp)
f4: 00812103 lw sp,8(sp)
f8: 00c12183 lw gp,12(sp)
fc: 01012203 lw tp,16(sp)
100: 01412283 lw t0,20(sp)
104: 01812303 lw t1,24(sp)
108: 01c12383 lw t2,28(sp)
10c: 02012403 lw s0,32(sp)
110: 02412483 lw s1,36(sp)
114: 02812503 lw a0,40(sp)
118: 02c12583 lw a1,44(sp)
11c: 03012603 lw a2,48(sp)
120: 03412683 lw a3,52(sp)
124: 03812703 lw a4,56(sp)
128: 03c12783 lw a5,60(sp)
12c: 04012803 lw a6,64(sp)
130: 04412883 lw a7,68(sp)
134: 04812903 lw s2,72(sp)
138: 04c12983 lw s3,76(sp)
13c: 05012a03 lw s4,80(sp)
140: 05412a83 lw s5,84(sp)
144: 05812b03 lw s6,88(sp)
148: 05c12b83 lw s7,92(sp)
14c: 06012c03 lw s8,96(sp)
150: 06412c83 lw s9,100(sp)
154: 06812d03 lw s10,104(sp)
158: 06c12d83 lw s11,108(sp)
15c: 07012e03 lw t3,112(sp)
160: 07412e83 lw t4,116(sp)
164: 07812f03 lw t5,120(sp)
168: 07c12f83 lw t6,124(sp)
16c: 08010113 addi sp,sp,128
170: 30200073 mret
174: 0000006f j 174 <trap_entry+0x10c>
00000178 <main>:
178: ff010113 addi sp,sp,-16
17c: 00112623 sw ra,12(sp)
180: 00812423 sw s0,8(sp)
184: 01010413 addi s0,sp,16
188: 688000ef jal ra,810 <uart_init>
18c: 10000517 auipc a0,0x10000
190: e7450513 addi a0,a0,-396 # 10000000 <_data>
194: 5d0000ef jal ra,764 <xprintf>
198: 0000006f j 198 <main+0x20>
0000019c <trap_handler>:
19c: fe010113 addi sp,sp,-32
1a0: 00112e23 sw ra,28(sp)
1a4: 00812c23 sw s0,24(sp)
1a8: 02010413 addi s0,sp,32
1ac: fea42623 sw a0,-20(s0)
1b0: 00000097 auipc ra,0x0
1b4: 000000e7 jalr zero # 0 <_start>
1b8: 00000013 nop
1bc: 01c12083 lw ra,28(sp)
1c0: 01812403 lw s0,24(sp)
1c4: 02010113 addi sp,sp,32
1c8: 00008067 ret
000001cc <_init>:
1cc: ff010113 addi sp,sp,-16
1d0: 00812623 sw s0,12(sp)
1d4: 01010413 addi s0,sp,16
1d8: 00000797 auipc a5,0x0
1dc: e9078793 addi a5,a5,-368 # 68 <trap_entry>
1e0: 30579073 csrw mtvec,a5
1e4: 00000013 nop
1e8: 00c12403 lw s0,12(sp)
1ec: 01010113 addi sp,sp,16
1f0: 00008067 ret
000001f4 <xputc>:
1f4: fe010113 addi sp,sp,-32
1f8: 00112e23 sw ra,28(sp)
1fc: 00812c23 sw s0,24(sp)
200: 02010413 addi s0,sp,32
204: 00050793 mv a5,a0
208: fef407a3 sb a5,-17(s0)
20c: 10000797 auipc a5,0x10000
210: e6478793 addi a5,a5,-412 # 10000070 <__bss_start>
214: 0007a783 lw a5,0(a5)
218: 02078663 beqz a5,244 <xputc+0x50>
21c: 10000797 auipc a5,0x10000
220: e5478793 addi a5,a5,-428 # 10000070 <__bss_start>
224: 0007a783 lw a5,0(a5)
228: 00178693 addi a3,a5,1
22c: 10000717 auipc a4,0x10000
230: e4470713 addi a4,a4,-444 # 10000070 <__bss_start>
234: 00d72023 sw a3,0(a4)
238: fef44703 lbu a4,-17(s0)
23c: 00e78023 sb a4,0(a5)
240: 02c0006f j 26c <xputc+0x78>
244: 10000797 auipc a5,0x10000
248: e3078793 addi a5,a5,-464 # 10000074 <xfunc_out>
24c: 0007a783 lw a5,0(a5)
250: 00078e63 beqz a5,26c <xputc+0x78>
254: 10000797 auipc a5,0x10000
258: e2078793 addi a5,a5,-480 # 10000074 <xfunc_out>
25c: 0007a703 lw a4,0(a5)
260: fef44783 lbu a5,-17(s0)
264: 00078513 mv a0,a5
268: 000700e7 jalr a4
26c: 01c12083 lw ra,28(sp)
270: 01812403 lw s0,24(sp)
274: 02010113 addi sp,sp,32
278: 00008067 ret
0000027c <xputs>:
27c: fe010113 addi sp,sp,-32
280: 00112e23 sw ra,28(sp)
284: 00812c23 sw s0,24(sp)
288: 02010413 addi s0,sp,32
28c: fea42623 sw a0,-20(s0)
290: 01c0006f j 2ac <xputs+0x30>
294: fec42783 lw a5,-20(s0)
298: 00178713 addi a4,a5,1
29c: fee42623 sw a4,-20(s0)
2a0: 0007c783 lbu a5,0(a5)
2a4: 00078513 mv a0,a5
2a8: f4dff0ef jal ra,1f4 <xputc>
2ac: fec42783 lw a5,-20(s0)
2b0: 0007c783 lbu a5,0(a5)
2b4: fe0790e3 bnez a5,294 <xputs+0x18>
2b8: 00000013 nop
2bc: 01c12083 lw ra,28(sp)
2c0: 01812403 lw s0,24(sp)
2c4: 02010113 addi sp,sp,32
2c8: 00008067 ret
000002cc <xvprintf>:
2cc: fb010113 addi sp,sp,-80
2d0: 04112623 sw ra,76(sp)
2d4: 04812423 sw s0,72(sp)
2d8: 05010413 addi s0,sp,80
2dc: faa42e23 sw a0,-68(s0)
2e0: fab42c23 sw a1,-72(s0)
2e4: fbc42783 lw a5,-68(s0)
2e8: 00178713 addi a4,a5,1
2ec: fae42e23 sw a4,-68(s0)
2f0: 0007c783 lbu a5,0(a5)
2f4: fcf40ba3 sb a5,-41(s0)
2f8: fd744783 lbu a5,-41(s0)
2fc: 44078463 beqz a5,744 <xvprintf+0x478>
300: fd744703 lbu a4,-41(s0)
304: 02500793 li a5,37
308: 00f70a63 beq a4,a5,31c <xvprintf+0x50>
30c: fd744783 lbu a5,-41(s0)
310: 00078513 mv a0,a5
314: ee1ff0ef jal ra,1f4 <xputc>
318: 4280006f j 740 <xvprintf+0x474>
31c: fc042e23 sw zero,-36(s0)
320: fbc42783 lw a5,-68(s0)
324: 00178713 addi a4,a5,1
328: fae42e23 sw a4,-68(s0)
32c: 0007c783 lbu a5,0(a5)
330: fcf40ba3 sb a5,-41(s0)
334: fd744703 lbu a4,-41(s0)
338: 03000793 li a5,48
33c: 02f71263 bne a4,a5,360 <xvprintf+0x94>
340: 00100793 li a5,1
344: fcf42e23 sw a5,-36(s0)
348: fbc42783 lw a5,-68(s0)
34c: 00178713 addi a4,a5,1
350: fae42e23 sw a4,-68(s0)
354: 0007c783 lbu a5,0(a5)
358: fcf40ba3 sb a5,-41(s0)
35c: 02c0006f j 388 <xvprintf+0xbc>
360: fd744703 lbu a4,-41(s0)
364: 02d00793 li a5,45
368: 02f71063 bne a4,a5,388 <xvprintf+0xbc>
36c: 00200793 li a5,2
370: fcf42e23 sw a5,-36(s0)
374: fbc42783 lw a5,-68(s0)
378: 00178713 addi a4,a5,1
37c: fae42e23 sw a4,-68(s0)
380: 0007c783 lbu a5,0(a5)
384: fcf40ba3 sb a5,-41(s0)
388: fe042023 sw zero,-32(s0)
38c: 0400006f j 3cc <xvprintf+0x100>
390: fe042703 lw a4,-32(s0)
394: 00070793 mv a5,a4
398: 00279793 slli a5,a5,0x2
39c: 00e787b3 add a5,a5,a4
3a0: 00179793 slli a5,a5,0x1
3a4: 00078713 mv a4,a5
3a8: fd744783 lbu a5,-41(s0)
3ac: 00f707b3 add a5,a4,a5
3b0: fd078793 addi a5,a5,-48
3b4: fef42023 sw a5,-32(s0)
3b8: fbc42783 lw a5,-68(s0)
3bc: 00178713 addi a4,a5,1
3c0: fae42e23 sw a4,-68(s0)
3c4: 0007c783 lbu a5,0(a5)
3c8: fcf40ba3 sb a5,-41(s0)
3cc: fd744703 lbu a4,-41(s0)
3d0: 02f00793 li a5,47
3d4: 00e7f863 bgeu a5,a4,3e4 <xvprintf+0x118>
3d8: fd744703 lbu a4,-41(s0)
3dc: 03900793 li a5,57
3e0: fae7f8e3 bgeu a5,a4,390 <xvprintf+0xc4>
3e4: fd744703 lbu a4,-41(s0)
3e8: 06c00793 li a5,108
3ec: 00f70863 beq a4,a5,3fc <xvprintf+0x130>
3f0: fd744703 lbu a4,-41(s0)
3f4: 04c00793 li a5,76
3f8: 02f71263 bne a4,a5,41c <xvprintf+0x150>
3fc: fdc42783 lw a5,-36(s0)
400: 0047e793 ori a5,a5,4
404: fcf42e23 sw a5,-36(s0)
408: fbc42783 lw a5,-68(s0)
40c: 00178713 addi a4,a5,1
410: fae42e23 sw a4,-68(s0)
414: 0007c783 lbu a5,0(a5)
418: fcf40ba3 sb a5,-41(s0)
41c: fd744783 lbu a5,-41(s0)
420: 32078663 beqz a5,74c <xvprintf+0x480>
424: fd744783 lbu a5,-41(s0)
428: fcf40b23 sb a5,-42(s0)
42c: fd644703 lbu a4,-42(s0)
430: 06000793 li a5,96
434: 00e7f863 bgeu a5,a4,444 <xvprintf+0x178>
438: fd644783 lbu a5,-42(s0)
43c: fe078793 addi a5,a5,-32
440: fcf40b23 sb a5,-42(s0)
444: fd644783 lbu a5,-42(s0)
448: fbe78793 addi a5,a5,-66
44c: 01600713 li a4,22
450: 10f76663 bltu a4,a5,55c <xvprintf+0x290>
454: 00279713 slli a4,a5,0x2
458: 10000797 auipc a5,0x10000
45c: bb878793 addi a5,a5,-1096 # 10000010 <_data+0x10>
460: 00f707b3 add a5,a4,a5
464: 0007a703 lw a4,0(a5)
468: 10000797 auipc a5,0x10000
46c: ba878793 addi a5,a5,-1112 # 10000010 <_data+0x10>
470: 00f707b3 add a5,a4,a5
474: 00078067 jr a5
478: fb842783 lw a5,-72(s0)
47c: 00478713 addi a4,a5,4
480: fae42c23 sw a4,-72(s0)
484: 0007a783 lw a5,0(a5)
488: fcf42823 sw a5,-48(s0)
48c: fe042223 sw zero,-28(s0)
490: 0100006f j 4a0 <xvprintf+0x1d4>
494: fe442783 lw a5,-28(s0)
498: 00178793 addi a5,a5,1
49c: fef42223 sw a5,-28(s0)
4a0: fd042703 lw a4,-48(s0)
4a4: fe442783 lw a5,-28(s0)
4a8: 00f707b3 add a5,a4,a5
4ac: 0007c783 lbu a5,0(a5)
4b0: fe0792e3 bnez a5,494 <xvprintf+0x1c8>
4b4: 00c0006f j 4c0 <xvprintf+0x1f4>
4b8: 02000513 li a0,32
4bc: d39ff0ef jal ra,1f4 <xputc>
4c0: fdc42783 lw a5,-36(s0)
4c4: 0027f793 andi a5,a5,2
4c8: 00079c63 bnez a5,4e0 <xvprintf+0x214>
4cc: fe442783 lw a5,-28(s0)
4d0: 00178713 addi a4,a5,1
4d4: fee42223 sw a4,-28(s0)
4d8: fe042703 lw a4,-32(s0)
4dc: fce7eee3 bltu a5,a4,4b8 <xvprintf+0x1ec>
4e0: fd042503 lw a0,-48(s0)
4e4: d99ff0ef jal ra,27c <xputs>
4e8: 00c0006f j 4f4 <xvprintf+0x228>
4ec: 02000513 li a0,32
4f0: d05ff0ef jal ra,1f4 <xputc>
4f4: fe442783 lw a5,-28(s0)
4f8: 00178713 addi a4,a5,1
4fc: fee42223 sw a4,-28(s0)
500: fe042703 lw a4,-32(s0)
504: fee7e4e3 bltu a5,a4,4ec <xvprintf+0x220>
508: 2380006f j 740 <xvprintf+0x474>
50c: fb842783 lw a5,-72(s0)
510: 00478713 addi a4,a5,4
514: fae42c23 sw a4,-72(s0)
518: 0007a783 lw a5,0(a5)
51c: 0ff7f793 andi a5,a5,255
520: 00078513 mv a0,a5
524: cd1ff0ef jal ra,1f4 <xputc>
528: 2180006f j 740 <xvprintf+0x474>
52c: 00200793 li a5,2
530: fef42623 sw a5,-20(s0)
534: 0380006f j 56c <xvprintf+0x2a0>
538: 00800793 li a5,8
53c: fef42623 sw a5,-20(s0)
540: 02c0006f j 56c <xvprintf+0x2a0>
544: 00a00793 li a5,10
548: fef42623 sw a5,-20(s0)
54c: 0200006f j 56c <xvprintf+0x2a0>
550: 01000793 li a5,16
554: fef42623 sw a5,-20(s0)
558: 0140006f j 56c <xvprintf+0x2a0>
55c: fd744783 lbu a5,-41(s0)
560: 00078513 mv a0,a5
564: c91ff0ef jal ra,1f4 <xputc>
568: 1d80006f j 740 <xvprintf+0x474>
56c: fdc42783 lw a5,-36(s0)
570: 0047f793 andi a5,a5,4
574: 00078c63 beqz a5,58c <xvprintf+0x2c0>
578: fb842783 lw a5,-72(s0)
57c: 00478713 addi a4,a5,4
580: fae42c23 sw a4,-72(s0)
584: 0007a783 lw a5,0(a5)
588: 0340006f j 5bc <xvprintf+0x2f0>
58c: fd644703 lbu a4,-42(s0)
590: 04400793 li a5,68
594: 00f71c63 bne a4,a5,5ac <xvprintf+0x2e0>
598: fb842783 lw a5,-72(s0)
59c: 00478713 addi a4,a5,4
5a0: fae42c23 sw a4,-72(s0)
5a4: 0007a783 lw a5,0(a5)
5a8: 0140006f j 5bc <xvprintf+0x2f0>
5ac: fb842783 lw a5,-72(s0)
5b0: 00478713 addi a4,a5,4
5b4: fae42c23 sw a4,-72(s0)
5b8: 0007a783 lw a5,0(a5)
5bc: fcf42c23 sw a5,-40(s0)
5c0: fd644703 lbu a4,-42(s0)
5c4: 04400793 li a5,68
5c8: 02f71263 bne a4,a5,5ec <xvprintf+0x320>
5cc: fd842783 lw a5,-40(s0)
5d0: 0007de63 bgez a5,5ec <xvprintf+0x320>
5d4: fd842783 lw a5,-40(s0)
5d8: 40f007b3 neg a5,a5
5dc: fcf42c23 sw a5,-40(s0)
5e0: fdc42783 lw a5,-36(s0)
5e4: 0087e793 ori a5,a5,8
5e8: fcf42e23 sw a5,-36(s0)
5ec: fe042423 sw zero,-24(s0)
5f0: fd842703 lw a4,-40(s0)
5f4: fec42783 lw a5,-20(s0)
5f8: 02f777b3 remu a5,a4,a5
5fc: fcf40b23 sb a5,-42(s0)
600: fd842703 lw a4,-40(s0)
604: fec42783 lw a5,-20(s0)
608: 02f757b3 divu a5,a4,a5
60c: fcf42c23 sw a5,-40(s0)
610: fd644703 lbu a4,-42(s0)
614: 00900793 li a5,9
618: 02e7f463 bgeu a5,a4,640 <xvprintf+0x374>
61c: fd744703 lbu a4,-41(s0)
620: 07800793 li a5,120
624: 00f71663 bne a4,a5,630 <xvprintf+0x364>
628: 02700793 li a5,39
62c: 0080006f j 634 <xvprintf+0x368>
630: 00700793 li a5,7
634: fd644703 lbu a4,-42(s0)
638: 00e787b3 add a5,a5,a4
63c: fcf40b23 sb a5,-42(s0)
640: fe842783 lw a5,-24(s0)
644: 00178713 addi a4,a5,1
648: fee42423 sw a4,-24(s0)
64c: fd644703 lbu a4,-42(s0)
650: 03070713 addi a4,a4,48
654: 0ff77713 andi a4,a4,255
658: ff040693 addi a3,s0,-16
65c: 00f687b3 add a5,a3,a5
660: fce78823 sb a4,-48(a5)
664: fd842783 lw a5,-40(s0)
668: 00078863 beqz a5,678 <xvprintf+0x3ac>
66c: fe842703 lw a4,-24(s0)
670: 00f00793 li a5,15
674: f6e7fee3 bgeu a5,a4,5f0 <xvprintf+0x324>
678: fdc42783 lw a5,-36(s0)
67c: 0087f793 andi a5,a5,8
680: 02078063 beqz a5,6a0 <xvprintf+0x3d4>
684: fe842783 lw a5,-24(s0)
688: 00178713 addi a4,a5,1
68c: fee42423 sw a4,-24(s0)
690: ff040713 addi a4,s0,-16
694: 00f707b3 add a5,a4,a5
698: 02d00713 li a4,45
69c: fce78823 sb a4,-48(a5)
6a0: fe842783 lw a5,-24(s0)
6a4: fef42223 sw a5,-28(s0)
6a8: fdc42783 lw a5,-36(s0)
6ac: 0017f793 andi a5,a5,1
6b0: 00078663 beqz a5,6bc <xvprintf+0x3f0>
6b4: 03000793 li a5,48
6b8: 0080006f j 6c0 <xvprintf+0x3f4>
6bc: 02000793 li a5,32
6c0: fcf40b23 sb a5,-42(s0)
6c4: 0100006f j 6d4 <xvprintf+0x408>
6c8: fd644783 lbu a5,-42(s0)
6cc: 00078513 mv a0,a5
6d0: b25ff0ef jal ra,1f4 <xputc>
6d4: fdc42783 lw a5,-36(s0)
6d8: 0027f793 andi a5,a5,2
6dc: 00079c63 bnez a5,6f4 <xvprintf+0x428>
6e0: fe442783 lw a5,-28(s0)
6e4: 00178713 addi a4,a5,1
6e8: fee42223 sw a4,-28(s0)
6ec: fe042703 lw a4,-32(s0)
6f0: fce7ece3 bltu a5,a4,6c8 <xvprintf+0x3fc>
6f4: fe842783 lw a5,-24(s0)
6f8: fff78793 addi a5,a5,-1
6fc: fef42423 sw a5,-24(s0)
700: fe842783 lw a5,-24(s0)
704: ff040713 addi a4,s0,-16
708: 00f707b3 add a5,a4,a5
70c: fd07c783 lbu a5,-48(a5)
710: 00078513 mv a0,a5
714: ae1ff0ef jal ra,1f4 <xputc>
718: fe842783 lw a5,-24(s0)
71c: fc079ce3 bnez a5,6f4 <xvprintf+0x428>
720: 00c0006f j 72c <xvprintf+0x460>
724: 02000513 li a0,32
728: acdff0ef jal ra,1f4 <xputc>
72c: fe442783 lw a5,-28(s0)
730: 00178713 addi a4,a5,1
734: fee42223 sw a4,-28(s0)
738: fe042703 lw a4,-32(s0)
73c: fee7e4e3 bltu a5,a4,724 <xvprintf+0x458>
740: ba5ff06f j 2e4 <xvprintf+0x18>
744: 00000013 nop
748: 0080006f j 750 <xvprintf+0x484>
74c: 00000013 nop
750: 00000013 nop
754: 04c12083 lw ra,76(sp)
758: 04812403 lw s0,72(sp)
75c: 05010113 addi sp,sp,80
760: 00008067 ret
00000764 <xprintf>:
764: fb010113 addi sp,sp,-80
768: 02112623 sw ra,44(sp)
76c: 02812423 sw s0,40(sp)
770: 03010413 addi s0,sp,48
774: fca42e23 sw a0,-36(s0)
778: 00b42223 sw a1,4(s0)
77c: 00c42423 sw a2,8(s0)
780: 00d42623 sw a3,12(s0)
784: 00e42823 sw a4,16(s0)
788: 00f42a23 sw a5,20(s0)
78c: 01042c23 sw a6,24(s0)
790: 01142e23 sw a7,28(s0)
794: 02040793 addi a5,s0,32
798: fe478793 addi a5,a5,-28
79c: fef42623 sw a5,-20(s0)
7a0: fec42783 lw a5,-20(s0)
7a4: 00078593 mv a1,a5
7a8: fdc42503 lw a0,-36(s0)
7ac: b21ff0ef jal ra,2cc <xvprintf>
7b0: 00000013 nop
7b4: 02c12083 lw ra,44(sp)
7b8: 02812403 lw s0,40(sp)
7bc: 05010113 addi sp,sp,80
7c0: 00008067 ret
000007c4 <uart_putc>:
7c4: fe010113 addi sp,sp,-32
7c8: 00812e23 sw s0,28(sp)
7cc: 02010413 addi s0,sp,32
7d0: 00050793 mv a5,a0
7d4: fef407a3 sb a5,-17(s0)
7d8: 00000013 nop
7dc: 300007b7 lui a5,0x30000
7e0: 00478793 addi a5,a5,4 # 30000004 <_sp+0x1fffd004>
7e4: 0007a783 lw a5,0(a5)
7e8: 0017f793 andi a5,a5,1
7ec: fe0798e3 bnez a5,7dc <uart_putc+0x18>
7f0: 300007b7 lui a5,0x30000
7f4: 00c78793 addi a5,a5,12 # 3000000c <_sp+0x1fffd00c>
7f8: fef44703 lbu a4,-17(s0)
7fc: 00e7a023 sw a4,0(a5)
800: 00000013 nop
804: 01c12403 lw s0,28(sp)
808: 02010113 addi sp,sp,32
80c: 00008067 ret
00000810 <uart_init>:
810: ff010113 addi sp,sp,-16
814: 00812623 sw s0,12(sp)
818: 01010413 addi s0,sp,16
81c: 300007b7 lui a5,0x30000
820: 00100713 li a4,1
824: 00e7a023 sw a4,0(a5) # 30000000 <_sp+0x1fffd000>
828: 10000797 auipc a5,0x10000
82c: 84c78793 addi a5,a5,-1972 # 10000074 <xfunc_out>
830: 00000717 auipc a4,0x0
834: f9470713 addi a4,a4,-108 # 7c4 <uart_putc>
838: 00e7a023 sw a4,0(a5)
83c: 00000013 nop
840: 00c12403 lw s0,12(sp)
844: 01010113 addi sp,sp,16
848: 00008067 ret
Disassembly of section .data:
10000000 <__global_pointer$-0x870>:
10000000: 6568 flw fa0,76(a0)
10000002: 6c6c flw fa1,92(s0)
10000004: 6f77206f j 10072efa <_sp+0x6fefa>
10000008: 6c72 flw fs8,28(sp)
1000000a: 0a64 addi s1,sp,284
1000000c: 0000 unimp
1000000e: 0000 unimp
10000010: 051c addi a5,sp,640
10000012: f000 fsw fs0,32(s0)
10000014: 04fc addi a5,sp,588
10000016: f000 fsw fs0,32(s0)
10000018: 0534 addi a3,sp,648
1000001a: f000 fsw fs0,32(s0)
1000001c: 054c addi a1,sp,644
1000001e: f000 fsw fs0,32(s0)
10000020: 054c addi a1,sp,644
10000022: f000 fsw fs0,32(s0)
10000024: 054c addi a1,sp,644
10000026: f000 fsw fs0,32(s0)
10000028: 054c addi a1,sp,644
1000002a: f000 fsw fs0,32(s0)
1000002c: 054c addi a1,sp,644
1000002e: f000 fsw fs0,32(s0)
10000030: 054c addi a1,sp,644
10000032: f000 fsw fs0,32(s0)
10000034: 054c addi a1,sp,644
10000036: f000 fsw fs0,32(s0)
10000038: 054c addi a1,sp,644
1000003a: f000 fsw fs0,32(s0)
1000003c: 054c addi a1,sp,644
1000003e: f000 fsw fs0,32(s0)
10000040: 054c addi a1,sp,644
10000042: f000 fsw fs0,32(s0)
10000044: 0528 addi a0,sp,648
10000046: f000 fsw fs0,32(s0)
10000048: 054c addi a1,sp,644
1000004a: f000 fsw fs0,32(s0)
1000004c: 054c addi a1,sp,644
1000004e: f000 fsw fs0,32(s0)
10000050: 054c addi a1,sp,644
10000052: f000 fsw fs0,32(s0)
10000054: 0468 addi a0,sp,524
10000056: f000 fsw fs0,32(s0)
10000058: 054c addi a1,sp,644
1000005a: f000 fsw fs0,32(s0)
1000005c: 0534 addi a3,sp,648
1000005e: f000 fsw fs0,32(s0)
10000060: 054c addi a1,sp,644
10000062: f000 fsw fs0,32(s0)
10000064: 054c addi a1,sp,644
10000066: f000 fsw fs0,32(s0)
10000068: 0540 addi s0,sp,644
1000006a: f000 fsw fs0,32(s0)
1000006c: 0000 unimp
...
Disassembly of section .bss:
10000070 <__bss_start>:
10000070: 0000 unimp
...
10000074 <xfunc_out>:
10000074: 0000 unimp
...
Disassembly of section .stack:
10002000 <_sp-0x1000>:
...
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <trap_entry+0x48>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <trap_entry+0x54>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...

7
tools/.gitignore vendored Normal file
View File

@ -0,0 +1,7 @@
# Object files
*.o
*.ko
*.obj
__pycache__
gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64

Binary file not shown.

Binary file not shown.