liangkangnan
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29623c8d2a
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rtl: div: fix error
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-14 22:22:42 +08:00 |
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liangkangnan
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8c3d7ac932
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rtl: div: timing optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-12 14:17:34 +08:00 |
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liangkangnan
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b57bfe7736
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rtl: timing optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-09 21:00:14 +08:00 |
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liangkangnan
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b6754f002c
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rtl: div: optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-06 23:17:56 +08:00 |
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liangkangnan
|
0ed81ff1a8
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rtl: remove unused signals
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-08-29 22:35:43 +08:00 |
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liangkangnan
|
10a3df3e5a
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rtl: core: fix sync interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-08-15 16:05:06 +08:00 |
Blue Liang
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fccb920070
|
rtl: core: optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-08-13 09:01:27 +08:00 |
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Blue Liang
|
fa958a6153
|
rtl: rib: arbitrated by logic instead of clock
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-08-13 08:56:01 +08:00 |
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liangkangnan
|
e23ad11e7e
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rtl: fix sync interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-25 22:15:03 +08:00 |
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liangkangnan
|
b39062a4ea
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rtl: fix interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-25 16:23:45 +08:00 |
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liangkangnan
|
a73b0ea36b
|
rtl: add uart_debug module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-04 14:32:31 +08:00 |
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liangkangnan
|
e28381dbcf
|
add support for ebreak inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-06-13 14:56:44 +08:00 |
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liangkangnan
|
5b888bd483
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rtl: core: fix data related for csr regs
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-06-05 22:22:49 +08:00 |
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liangkangnan
|
eec414aa96
|
use = instead of <=
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-31 14:38:57 +08:00 |
|
liangkangnan
|
260246f488
|
fix nop inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-07 22:40:31 +08:00 |
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liangkangnan
|
07b33baf94
|
perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-05 18:31:08 +08:00 |
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liangkangnan
|
837af2c977
|
use = instead of <= in combination logic
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-02 11:58:44 +08:00 |
|
liangkangnan
|
aead35700c
|
add signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:15:46 +08:00 |
|
liangkangnan
|
02d19b9e6f
|
add mie and mstatus reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:13:12 +08:00 |
|
liangkangnan
|
4a530ab894
|
add ECALL inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:11:53 +08:00 |
|
liangkangnan
|
43aca8195c
|
add clint hold input signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:08:46 +08:00 |
|
liangkangnan
|
6cf86e0286
|
stop div when interrupt assert
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:04:44 +08:00 |
|
liangkangnan
|
09513f8f2c
|
support preemption
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:03:13 +08:00 |
|
liangkangnan
|
dcac95dfab
|
add code comments
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 20:14:37 +08:00 |
|
liangkangnan
|
ce225394df
|
fix reg1 reg2 bits width
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:35:43 +08:00 |
|
liangkangnan
|
b29781a8de
|
optimize div
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:23:46 +08:00 |
|
liangkangnan
|
2638240d0b
|
add mepc reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:22:20 +08:00 |
|
liangkangnan
|
96f8d6e5a0
|
optimized: use statemachine
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:21:09 +08:00 |
|
liangkangnan
|
0e188d4934
|
reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-11 19:03:49 +08:00 |
|
liangkangnan
|
a68f31b604
|
perips: add uart_tx and gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-05 22:27:00 +08:00 |
|
liangkangnan
|
6660f18b3d
|
support CSR inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-05 22:22:34 +08:00 |
|
liangkangnan
|
ecb9fca8c1
|
update
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-29 23:19:14 +08:00 |
|
liangkangnan
|
8b51737477
|
add interrupt support and example
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-08 15:09:30 +08:00 |
|
liangkangnan
|
8208cbc100
|
support JTAG
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-01 14:55:36 +08:00 |