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188 Commits
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72 Commits (ad775ef316e8455a99878dbd4596aa9f9e1be2f7)

Author SHA1 Message Date
liangkangnan ad775ef316 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-09 20:27:33 +08:00
liangkangnan f1f09584ee optimize ifu and lsu 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-09 20:22:34 +08:00
liangkangnan e3667e0ddd temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-01 11:29:00 +08:00
liangkangnan 9943d02600 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-31 18:00:19 +08:00
liangkangnan c070f0b49d temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-31 15:25:22 +08:00
Blue Liang 8214134b89 tmp commit, unstable 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 15:14:50 +08:00
liangkangnan fdc776ab5e rtl: debug: support reset cmd 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-12-06 20:06:12 +08:00
liangkangnan f03f42fc9b rtl: add reset ctrl module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-18 22:15:08 +08:00
liangkangnan 5c9f1a140e rtl: add mem access misaligned exception 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-08 22:08:03 +08:00
Blue Liang 60a4f7d6df rtl: add generate block name 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-26 17:01:04 +08:00
liangkangnan 2b44f1e8f3 first release 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-23 21:26:18 +08:00
liangkangnan 4876225f60 rtl: utils: add full handshake CDC source 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-23 21:39:20 +08:00
liangkangnan 386ba909ba rtl: jtag: handle DM module in cpu clock domain 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-23 21:37:00 +08:00
liangkangnan 633a1d0b15 rtl: debug: fix latch 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-20 22:18:58 +08:00
liangkangnan 29623c8d2a rtl: div: fix error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-14 22:22:42 +08:00
liangkangnan 045f482fe1 rtl: jtag: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-13 17:47:18 +08:00
liangkangnan 8c3d7ac932 rtl: div: timing optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:17:34 +08:00
liangkangnan 8468303ba7 rtl: add gen_buf.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:14:59 +08:00
liangkangnan b57bfe7736 rtl: timing optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 21:00:14 +08:00
liangkangnan a4a723e1e7 rtl: add gen_dff.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 20:58:08 +08:00
liangkangnan b6754f002c rtl: div: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-06 23:17:56 +08:00
liangkangnan 0ed81ff1a8 rtl: remove unused signals 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-29 22:35:43 +08:00
liangkangnan 10a3df3e5a rtl: core: fix sync interrupt 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-15 16:05:06 +08:00
Blue Liang fccb920070 rtl: core: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-13 09:01:27 +08:00
Blue Liang fa958a6153 rtl: rib: arbitrated by logic instead of clock 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-13 08:56:01 +08:00
liangkangnan e23ad11e7e rtl: fix sync interrupt return address 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 22:15:03 +08:00
liangkangnan b39062a4ea rtl: fix interrupt return address 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 16:23:45 +08:00
liangkangnan b0c4d1fa4d rtl:timer: update interrupt assert 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-12 22:33:15 +08:00
liangkangnan a73b0ea36b rtl: add uart_debug module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:32:31 +08:00
liangkangnan 4c6c044afb rtl: add uart rx function 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-26 22:40:44 +08:00
liangkangnan 2619f26eae gpio: add input function 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-14 10:40:25 +08:00
liangkangnan e28381dbcf add support for ebreak inst 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-13 14:56:44 +08:00
liangkangnan 5b888bd483 rtl: core: fix data related for csr regs 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-05 22:22:49 +08:00
liangkangnan de9a978417 fix: must exit openocd after download temporary 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-31 14:41:39 +08:00
liangkangnan eec414aa96 use = instead of <= 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-31 14:38:57 +08:00
liangkangnan 834fcfb3ef debug: optimization for jtag 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-13 21:27:40 +08:00
liangkangnan 260246f488 fix nop inst 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-07 22:40:31 +08:00
liangkangnan 07b33baf94 perips: add spi master 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-05 18:31:08 +08:00
liangkangnan 837af2c977 use = instead of <= in combination logic 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-02 11:58:44 +08:00
liangkangnan 043bc23f8a use = instead of <= in combination logic 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-02 11:57:25 +08:00
liangkangnan d7bdc35911 fix uninitial reg var 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-02 11:53:48 +08:00
liangkangnan aead35700c add signal 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:15:46 +08:00
liangkangnan d92352e1c2 use relative include path 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:15:00 +08:00
liangkangnan 02d19b9e6f add mie and mstatus reg 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:13:12 +08:00
liangkangnan 4a530ab894 add ECALL inst 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:11:53 +08:00
liangkangnan 02bcee9aa9 sync for different clock 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:10:11 +08:00
liangkangnan 43aca8195c add clint hold input signal 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:08:46 +08:00
liangkangnan 6cf86e0286 stop div when interrupt assert 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:04:44 +08:00
liangkangnan 09513f8f2c support preemption 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-25 17:03:13 +08:00
liangkangnan dcac95dfab add code comments 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-18 20:14:37 +08:00