liangkangnan
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15928977e1
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rtl:perips: add flash_ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-11-02 10:54:37 +08:00 |
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liangkangnan
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22a038cc09
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rtl🔝 add more perips
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-10 09:57:39 +08:00 |
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liangkangnan
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57690b00bd
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rtl:perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-06 10:01:56 +08:00 |
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liangkangnan
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ae3ff5a211
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rtl🚌 use gnt and rvalid signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-01 09:54:32 +08:00 |
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liangkangnan
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92e1e5a77a
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sim: add dump wave enable by softwave
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-20 11:50:21 +08:00 |
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liangkangnan
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3f400f2fb8
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tmp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-19 17:45:45 +08:00 |
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liangkangnan
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2afcba47ea
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rtl:perips: add i2c master
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-19 09:43:12 +08:00 |
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liangkangnan
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d4b670217a
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rtl:perips: rewrite rvic
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-14 14:03:47 +08:00 |
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liangkangnan
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5fa659a084
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rtl:perips: rewrite gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-13 09:33:15 +08:00 |
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liangkangnan
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64041b4d2b
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rtl: perips: rewrite timer module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-10 09:47:37 +08:00 |
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liangkangnan
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58f180a92f
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rtl: perips: rewrite uart module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-07 14:28:46 +08:00 |
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liangkangnan
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3227fb1ffd
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rtl:perips: add rvic
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-22 09:36:04 +08:00 |
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liangkangnan
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fd2c981317
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-09 15:18:09 +08:00 |
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liangkangnan
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6121a21322
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rtl: top: make jtag host highest priority
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 19:59:07 +08:00 |
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liangkangnan
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fb461a6176
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 11:45:53 +08:00 |
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liangkangnan
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a67fba652d
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add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-20 11:05:39 +08:00 |
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liangkangnan
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6e466fbbf7
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add perips
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 21:00:57 +08:00 |
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liangkangnan
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5811bdde13
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debug: add hw breakpoint support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 14:37:47 +08:00 |
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liangkangnan
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10d8d35a13
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rtl: fix combilation loop
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-02 14:51:12 +08:00 |
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liangkangnan
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53865371ce
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 16:41:24 +08:00 |
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liangkangnan
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f9412fca3c
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-29 19:27:25 +08:00 |
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liangkangnan
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ec65381ba9
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-25 17:14:09 +08:00 |
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liangkangnan
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05e2441d24
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 16:34:00 +08:00 |
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liangkangnan
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9ac1b31965
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rtl: add reset module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 14:12:47 +08:00 |
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liangkangnan
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7803e89d68
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 11:10:06 +08:00 |
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liangkangnan
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bd2d372c66
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-12 19:18:35 +08:00 |
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liangkangnan
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f1f09584ee
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optimize ifu and lsu
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:22:34 +08:00 |
Blue Liang
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8214134b89
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tmp commit, unstable
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 15:14:50 +08:00 |
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liangkangnan
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f03f42fc9b
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rtl: add reset ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-11-18 22:15:08 +08:00 |
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liangkangnan
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2b44f1e8f3
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first release
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-23 21:26:18 +08:00 |