liangkangnan
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4436e0cc6a
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tools: update openocd for win
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 19:48:41 +08:00 |
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liangkangnan
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b7b8572542
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tb: add tests type macro
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 16:59:26 +08:00 |
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liangkangnan
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d9a1f89fd2
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tests: riscv-compliance: add support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 16:02:02 +08:00 |
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liangkangnan
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6059c4c3a7
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tests: isa: add support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 15:11:33 +08:00 |
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liangkangnan
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c847244c5b
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rtl: perips: fix machine timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-03 09:23:50 +08:00 |
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liangkangnan
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646bc96419
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openocd: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-31 14:07:36 +08:00 |
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liangkangnan
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6d8015727e
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-31 10:27:01 +08:00 |
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liangkangnan
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247a5b6354
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-28 15:10:37 +08:00 |
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liangkangnan
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cd9ac0adae
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debug: change dmi addr bits to 7
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-28 10:37:50 +08:00 |
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liangkangnan
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fb461a6176
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 11:45:53 +08:00 |
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liangkangnan
|
c6163aaff1
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 09:41:00 +08:00 |
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liangkangnan
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fd5413791d
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example: coremark: print tips after uart init
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-22 15:26:24 +08:00 |
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liangkangnan
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87849fbd35
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README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 17:08:46 +08:00 |
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liangkangnan
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5353371516
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doc: add obi spec
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 17:06:39 +08:00 |
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liangkangnan
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bffeebd0bf
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example:simple: add -g flag
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 17:05:56 +08:00 |
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liangkangnan
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b98e1c5538
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bsp: use self-build gcc
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 14:19:50 +08:00 |
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liangkangnan
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af63e677d9
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example: fix freertos
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 09:50:21 +08:00 |
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liangkangnan
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01c3159a83
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use larger ram
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 09:43:34 +08:00 |
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liangkangnan
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a67fba652d
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add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-20 11:05:39 +08:00 |
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liangkangnan
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5efa66ee64
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debug: fix breakpoint
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 19:09:17 +08:00 |
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liangkangnan
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c7a374acb8
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 16:09:39 +08:00 |
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liangkangnan
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f08fd1b17e
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debug: fix step
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 15:35:11 +08:00 |
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liangkangnan
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6cd6532423
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example: add uart loopback
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 16:56:52 +08:00 |
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liangkangnan
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136dc45a09
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change core clock to 25MHZ
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 16:40:25 +08:00 |
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liangkangnan
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536d28ede3
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 10:22:04 +08:00 |
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liangkangnan
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b0f4592322
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-15 14:52:30 +08:00 |
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liangkangnan
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6e466fbbf7
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add perips
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 21:00:57 +08:00 |
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liangkangnan
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5811bdde13
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debug: add hw breakpoint support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 14:37:47 +08:00 |
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liangkangnan
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b02b38bddc
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-11 16:21:58 +08:00 |
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liangkangnan
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36147d9391
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-11 10:35:36 +08:00 |
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liangkangnan
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4a4c08bc69
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-04 21:11:43 +08:00 |
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liangkangnan
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10d8d35a13
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rtl: fix combilation loop
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-02 14:51:12 +08:00 |
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liangkangnan
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738fba1d6f
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 18:27:30 +08:00 |
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liangkangnan
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53865371ce
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 16:41:24 +08:00 |
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liangkangnan
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dfa8bf490e
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bus: fix bug
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 08:59:10 +08:00 |
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liangkangnan
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f9412fca3c
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-29 19:27:25 +08:00 |
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liangkangnan
|
77812d60df
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-26 14:08:26 +08:00 |
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liangkangnan
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4da79b6046
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debug: add sba module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-26 09:48:19 +08:00 |
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liangkangnan
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65a26842c4
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-25 19:34:21 +08:00 |
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liangkangnan
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ec65381ba9
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-25 17:14:09 +08:00 |
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liangkangnan
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462cc4c786
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 19:49:09 +08:00 |
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liangkangnan
|
05e2441d24
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 16:34:00 +08:00 |
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liangkangnan
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9ac1b31965
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rtl: add reset module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 14:12:47 +08:00 |
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liangkangnan
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7803e89d68
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 11:10:06 +08:00 |
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liangkangnan
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e53f681063
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rtl: optimize csr regs
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 09:25:29 +08:00 |
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liangkangnan
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bd2d372c66
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-12 19:18:35 +08:00 |
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liangkangnan
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16fa475ba7
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rtl:perips: remove vld rdy signals
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:47:00 +08:00 |
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liangkangnan
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ad775ef316
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:27:33 +08:00 |
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liangkangnan
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f1f09584ee
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optimize ifu and lsu
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:22:34 +08:00 |
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liangkangnan
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e3667e0ddd
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-01 11:29:00 +08:00 |