liangkangnan
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d92352e1c2
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use relative include path
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:15:00 +08:00 |
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liangkangnan
|
02d19b9e6f
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add mie and mstatus reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:13:12 +08:00 |
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liangkangnan
|
4a530ab894
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add ECALL inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:11:53 +08:00 |
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liangkangnan
|
02bcee9aa9
|
sync for different clock
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:10:11 +08:00 |
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liangkangnan
|
43aca8195c
|
add clint hold input signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:08:46 +08:00 |
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liangkangnan
|
6cf86e0286
|
stop div when interrupt assert
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:04:44 +08:00 |
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liangkangnan
|
09513f8f2c
|
support preemption
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:03:13 +08:00 |
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liangkangnan
|
dcac95dfab
|
add code comments
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 20:14:37 +08:00 |
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liangkangnan
|
18577d9b61
|
use oneshot mode
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 11:37:22 +08:00 |
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liangkangnan
|
ce225394df
|
fix reg1 reg2 bits width
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 11:35:43 +08:00 |
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liangkangnan
|
b29781a8de
|
optimize div
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:23:46 +08:00 |
|
liangkangnan
|
2638240d0b
|
add mepc reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:22:20 +08:00 |
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liangkangnan
|
96f8d6e5a0
|
optimized: use statemachine
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:21:09 +08:00 |
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liangkangnan
|
0e188d4934
|
reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-11 19:03:49 +08:00 |
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liangkangnan
|
b2827b2fb4
|
uart: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-06 19:54:40 +08:00 |
|
liangkangnan
|
e714a0ba63
|
add write dpc
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-06 14:34:12 +08:00 |
|
liangkangnan
|
a68f31b604
|
perips: add uart_tx and gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-05 22:27:00 +08:00 |
|
liangkangnan
|
6660f18b3d
|
support CSR inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-05 22:22:34 +08:00 |
|
liangkangnan
|
ecb9fca8c1
|
update
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-29 23:19:14 +08:00 |
|
liangkangnan
|
8b51737477
|
add interrupt support and example
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-08 15:09:30 +08:00 |
|
liangkangnan
|
c7c9193982
|
add peripheral: timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-08 15:07:17 +08:00 |
|
liangkangnan
|
8208cbc100
|
support JTAG
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-01 14:55:36 +08:00 |
|
liangkangnan
|
0d4e8bb5f4
|
improve ex module
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-23 17:51:55 +08:00 |
|
liangkangnan
|
076610fb0d
|
rename openriscv to tinyriscv
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-23 17:01:45 +08:00 |
|
liangkangnan
|
97c7cee0ad
|
return to IDLE state when div completed
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-22 20:38:16 +08:00 |
|
liangkangnan
|
3b1807c467
|
fix: multi drive error
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-22 15:24:10 +08:00 |
|
liangkangnan
|
f0bd0845d6
|
fix implementation error by EDA tool
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-16 21:27:11 +08:00 |
|
Blue Liang
|
9420b85796
|
add div inst
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2020-01-13 08:26:41 +08:00 |
|
Blue Liang
|
97efd66e78
|
add mul instruction
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2020-01-02 16:12:13 +08:00 |
|
Blue Liang
|
ac995f0b01
|
first release
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2019-12-04 08:47:19 +08:00 |