liangkangnan
|
18de7f2e00
|
test: use csr_sstatus for test result
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-07-10 14:49:36 +08:00 |
|
liangkangnan
|
fd2c981317
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-07-09 15:18:09 +08:00 |
|
liangkangnan
|
b7b8572542
|
tb: add tests type macro
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-06-05 16:59:26 +08:00 |
|
liangkangnan
|
fb461a6176
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-05-25 11:45:53 +08:00 |
|
liangkangnan
|
a67fba652d
|
add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-05-20 11:05:39 +08:00 |
|
liangkangnan
|
c7a374acb8
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-05-19 16:09:39 +08:00 |
|
liangkangnan
|
4a4c08bc69
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-05-04 21:11:43 +08:00 |
|
liangkangnan
|
f9412fca3c
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-04-29 19:27:25 +08:00 |
|
liangkangnan
|
ec65381ba9
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-04-25 17:14:09 +08:00 |
|
liangkangnan
|
9ac1b31965
|
rtl: add reset module
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-04-13 14:12:47 +08:00 |
|
liangkangnan
|
c070f0b49d
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-03-31 15:25:22 +08:00 |
Blue Liang
|
8214134b89
|
tmp commit, unstable
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-03-29 15:14:50 +08:00 |