liangkangnan
|
15f10fbf35
|
sim: add uart_debug.v
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-04 17:21:50 +08:00 |
|
liangkangnan
|
1486b5aca8
|
sim: change uart_tx.v to uart.v
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-26 22:44:14 +08:00 |
|
liangkangnan
|
38c2245218
|
sim: remove tb file to tb dir
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-27 23:17:05 +08:00 |
|
liangkangnan
|
07b33baf94
|
perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-05 18:31:08 +08:00 |
|
liangkangnan
|
0e188d4934
|
reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-11 19:03:49 +08:00 |
|
liangkangnan
|
a68f31b604
|
perips: add uart_tx and gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-05 22:27:00 +08:00 |
|
liangkangnan
|
ecb9fca8c1
|
update
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-29 23:19:14 +08:00 |
|
liangkangnan
|
c7c9193982
|
add peripheral: timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-08 15:07:17 +08:00 |
|
liangkangnan
|
8208cbc100
|
support JTAG
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-01 14:55:36 +08:00 |
|
liangkangnan
|
076610fb0d
|
rename openriscv to tinyriscv
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-23 17:01:45 +08:00 |
|
Blue Liang
|
9420b85796
|
add div inst
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2020-01-13 08:26:41 +08:00 |
|
Blue Liang
|
ac995f0b01
|
first release
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2019-12-04 08:47:19 +08:00 |