liangkangnan
|
18de7f2e00
|
test: use csr_sstatus for test result
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-10 14:49:36 +08:00 |
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liangkangnan
|
fd2c981317
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-09 15:18:09 +08:00 |
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liangkangnan
|
b7b8572542
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tb: add tests type macro
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-06-05 16:59:26 +08:00 |
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liangkangnan
|
fb461a6176
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 11:45:53 +08:00 |
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liangkangnan
|
a67fba652d
|
add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-20 11:05:39 +08:00 |
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liangkangnan
|
c7a374acb8
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 16:09:39 +08:00 |
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liangkangnan
|
5811bdde13
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debug: add hw breakpoint support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 14:37:47 +08:00 |
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liangkangnan
|
36147d9391
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-11 10:35:36 +08:00 |
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liangkangnan
|
4a4c08bc69
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-04 21:11:43 +08:00 |
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liangkangnan
|
53865371ce
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 16:41:24 +08:00 |
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liangkangnan
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f9412fca3c
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-29 19:27:25 +08:00 |
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liangkangnan
|
ec65381ba9
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-25 17:14:09 +08:00 |
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liangkangnan
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9ac1b31965
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rtl: add reset module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 14:12:47 +08:00 |
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liangkangnan
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f1f09584ee
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optimize ifu and lsu
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:22:34 +08:00 |
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liangkangnan
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c070f0b49d
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-31 15:25:22 +08:00 |
Blue Liang
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8214134b89
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tmp commit, unstable
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 15:14:50 +08:00 |
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liangkangnan
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5c87fc09ef
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tb: add jtag testbench
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-12-06 20:07:06 +08:00 |
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liangkangnan
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f03f42fc9b
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rtl: add reset ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-11-18 22:15:08 +08:00 |
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liangkangnan
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eb5647915a
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python scripts: remove verison
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-25 12:02:26 +08:00 |
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liangkangnan
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2b44f1e8f3
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first release
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-23 21:26:18 +08:00 |
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liangkangnan
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b15a130862
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sim: compliance_test: add utils modules
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-06 21:00:04 +08:00 |
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liangkangnan
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4876225f60
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rtl: utils: add full handshake CDC source
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-23 21:39:20 +08:00 |
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liangkangnan
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90f57951e4
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sim: add gen_buf.v
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-12 14:16:02 +08:00 |
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liangkangnan
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5e4ab8c33c
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sim: add gen_dff.v
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-09 20:59:22 +08:00 |
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liangkangnan
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15f10fbf35
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sim: add uart_debug.v
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-04 17:21:50 +08:00 |
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Blue Liang
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4813893a34
|
sim: compliance_test: compare files line by line
Signed-off-by: Blue Liang <liangkangnan@163.com>
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2020-06-28 20:26:12 +08:00 |
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liangkangnan
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1486b5aca8
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sim: change uart_tx.v to uart.v
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-06-26 22:44:14 +08:00 |
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liangkangnan
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c3e607ec55
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sim: compliance_test: fix can not find ref file
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-06-05 22:16:36 +08:00 |
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liangkangnan
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dfbb1ed6c1
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sim: compliance_test: add README.md
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-27 23:47:55 +08:00 |
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liangkangnan
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8cb261b079
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sim: add README.md
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-27 23:43:35 +08:00 |
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liangkangnan
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38c2245218
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sim: remove tb file to tb dir
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-27 23:17:05 +08:00 |
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liangkangnan
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f775abf1d7
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sim: add compliance test script
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-27 23:08:43 +08:00 |
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liangkangnan
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edee04cfe2
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sim: fix vivado error
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-21 21:53:08 +08:00 |
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liangkangnan
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07b33baf94
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perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-05 18:31:08 +08:00 |
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liangkangnan
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0e188d4934
|
reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-11 19:03:49 +08:00 |
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liangkangnan
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20d1055ea4
|
example: reorganization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-06 21:28:56 +08:00 |
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liangkangnan
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a68f31b604
|
perips: add uart_tx and gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-05 22:27:00 +08:00 |
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liangkangnan
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ecb9fca8c1
|
update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-29 23:19:14 +08:00 |
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liangkangnan
|
a4148afa4d
|
update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-08 15:29:53 +08:00 |
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liangkangnan
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8b51737477
|
add interrupt support and example
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-08 15:09:30 +08:00 |
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liangkangnan
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c7c9193982
|
add peripheral: timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-08 15:07:17 +08:00 |
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liangkangnan
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8208cbc100
|
support JTAG
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-01 14:55:36 +08:00 |
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liangkangnan
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076610fb0d
|
rename openriscv to tinyriscv
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-02-23 17:01:45 +08:00 |
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Blue Liang
|
9420b85796
|
add div inst
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2020-01-13 08:26:41 +08:00 |
|
Blue Liang
|
ac995f0b01
|
first release
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2019-12-04 08:47:19 +08:00 |