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Commit Graph

144 Commits (22407f4b1fe83b89061f70e18dc66cac97a7bf4f)

Author SHA1 Message Date
liangkangnan 4c16dfb254 rtl: move top module into fpga dir 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2022-08-10 08:13:38 +08:00
liangkangnan 4958cb66c2 rtl: top: move out sim_jtag module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2022-08-06 14:32:56 +08:00
liangkangnan 3120110be3 rtl:core: ifu support for boot from flash 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-11-25 09:00:09 +08:00
liangkangnan 4720d020e4 rtl:perips:flash_ctrl: fix read state 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-11-16 15:24:37 +08:00
liangkangnan 15928977e1 rtl:perips: add flash_ctrl module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-11-02 10:54:37 +08:00
liangkangnan 274b19363b rtl:perips:spi: fix ss delay ctrl by sw 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-11-01 09:55:10 +08:00
liangkangnan 1e510dab9d rtl: utils: add up_counter module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-11-01 09:52:46 +08:00
liangkangnan b6d3b39f4d rtl:perips:spi: add fifo reset 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-10-12 10:22:02 +08:00
liangkangnan 3903d9e7f4 rtl:pinmux: add more spi mux 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-17 09:06:47 +08:00
liangkangnan 22a038cc09 rtl🔝 add more perips 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-10 09:57:39 +08:00
liangkangnan 55f37e93fa rtl:perips:gpio: increase to 16 gpios 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-10 09:51:08 +08:00
liangkangnan 4086a2d863 rtl:perips: add pinmux 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-10 09:48:44 +08:00
liangkangnan 57690b00bd rtl:perips: add spi master 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-06 10:01:56 +08:00
liangkangnan f74f2d8f5d rtl:utils:edge_detect: add DP parameter 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-01 14:14:36 +08:00
liangkangnan 574708bd89 rtl:utils:gen_buf: add handle for DP=0 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-01 14:12:21 +08:00
liangkangnan ae3ff5a211 rtl🚌 use gnt and rvalid signal 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-01 09:54:32 +08:00
liangkangnan 2c11873056 rtl:i2c: fix slave read error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-26 09:25:18 +08:00
liangkangnan e708eb6d4d rtl:perips:i2c: add i2c slave 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-25 17:51:35 +08:00
liangkangnan 7e57d8db17 rtl:perips:rvic: bug fix 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-25 17:47:18 +08:00
liangkangnan 92e1e5a77a sim: add dump wave enable by softwave 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-20 11:50:21 +08:00
liangkangnan 3f400f2fb8 tmp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-19 17:45:45 +08:00
liangkangnan 2afcba47ea rtl:perips: add i2c master 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-19 09:43:12 +08:00
liangkangnan 6143d9ee6a rtl:gpio: remove gpio.h 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-17 10:20:30 +08:00
liangkangnan d4b670217a rtl:perips: rewrite rvic 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-14 14:03:47 +08:00
liangkangnan 5fa659a084 rtl:perips: rewrite gpio 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-13 09:33:15 +08:00
liangkangnan 64041b4d2b rtl: perips: rewrite timer module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-10 09:47:37 +08:00
liangkangnan 58f180a92f rtl: perips: rewrite uart module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-07 14:28:46 +08:00
liangkangnan cba47c1f64 use none-vector interrupt mode 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-26 09:54:38 +08:00
liangkangnan 3227fb1ffd rtl:perips: add rvic 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-22 09:36:04 +08:00
liangkangnan 18de7f2e00 test: use csr_sstatus for test result 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-10 14:49:36 +08:00
liangkangnan fd2c981317 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-09 15:18:09 +08:00
liangkangnan 53e4263706 rtl: ifu optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-03 15:09:13 +08:00
liangkangnan 34218536c1 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-01 09:46:56 +08:00
liangkangnan 3269041c0b rtl: add config for branch predictor 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-28 11:31:04 +08:00
liangkangnan 2db9e7dbb9 rtl: add sync_fifo module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-28 11:09:37 +08:00
liangkangnan 96d6976c44 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-19 16:33:50 +08:00
liangkangnan 5f56e8d0fb temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-18 20:04:46 +08:00
liangkangnan 7196d33074 rtl: add static branch predict unit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-11 09:44:26 +08:00
liangkangnan f9f78976fb rtl: core: optimize mem access 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-05 20:00:15 +08:00
liangkangnan 6121a21322 rtl: top: make jtag host highest priority 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-05 19:59:07 +08:00
liangkangnan c847244c5b rtl: perips: fix machine timer 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-03 09:23:50 +08:00
liangkangnan 6d8015727e temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-31 10:27:01 +08:00
liangkangnan 247a5b6354 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-28 15:10:37 +08:00
liangkangnan cd9ac0adae debug: change dmi addr bits to 7 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-28 10:37:50 +08:00
liangkangnan fb461a6176 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-25 11:45:53 +08:00
liangkangnan c6163aaff1 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-25 09:41:00 +08:00
liangkangnan 01c3159a83 use larger ram 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-21 09:43:34 +08:00
liangkangnan a67fba652d add mmcm module for xilinx fpga 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-20 11:05:39 +08:00
liangkangnan 5efa66ee64 debug: fix breakpoint 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-19 19:09:17 +08:00
liangkangnan f08fd1b17e debug: fix step 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-19 15:35:11 +08:00