liangkangnan
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5c9f1a140e
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rtl: add mem access misaligned exception
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-11-08 22:08:03 +08:00 |
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liangkangnan
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2b44f1e8f3
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first release
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-23 21:26:18 +08:00 |
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liangkangnan
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10a3df3e5a
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rtl: core: fix sync interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-08-15 16:05:06 +08:00 |
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liangkangnan
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e23ad11e7e
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rtl: fix sync interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-25 22:15:03 +08:00 |
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liangkangnan
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b39062a4ea
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rtl: fix interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-25 16:23:45 +08:00 |
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liangkangnan
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e28381dbcf
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add support for ebreak inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-06-13 14:56:44 +08:00 |
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liangkangnan
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837af2c977
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use = instead of <= in combination logic
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-02 11:58:44 +08:00 |
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liangkangnan
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09513f8f2c
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support preemption
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:03:13 +08:00 |
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liangkangnan
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dcac95dfab
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add code comments
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 20:14:37 +08:00 |
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liangkangnan
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96f8d6e5a0
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optimized: use statemachine
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-18 11:21:09 +08:00 |
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liangkangnan
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0e188d4934
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reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-11 19:03:49 +08:00 |
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liangkangnan
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ecb9fca8c1
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update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-29 23:19:14 +08:00 |