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rtl: debug: support reset cmd 

Signed-off-by: liangkangnan <liangkangnan@163.com>
bram
liangkangnan 2020-12-06 20:06:12 +08:00
parent f03f42fc9b
commit fdc776ab5e
3 changed files with 19 additions and 14 deletions
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1
rtl/core/defines.v
View File

@ -18,6 +18,7 @@
`define CPU_CLOCK_HZ 50000000 // CPU时钟(50MHZ)
`define INST_MEM_START_ADDR 32'h0 // 指令存储器起始地址
`define INST_MEM_END_ADDR 32'h0fffffff // 指令存储器结束地址
`define JTAG_RESET_FF_LEVELS 5
`define ROM_DEPTH 8192 // 指令存储器深度，单位为word(4字节)
`define RAM_DEPTH 4096 // 数据存储器深度，单位为word(4字节)

16
rtl/core/rst_ctrl.v
View File

@ -14,6 +14,8 @@
limitations under the License.
*/
`include "defines.v"
// 复位控制模块
module rst_ctrl(
@ -39,17 +41,19 @@ module rst_ctrl(
.dout(ext_rst_r)
);
reg jtag_rst_r;
reg[`JTAG_RESET_FF_LEVELS-1:0] jtag_rst_r;
always @ (posedge clk or posedge rst_jtag_i) begin
if (rst_jtag_i) begin
jtag_rst_r <= 1'b0;
always @ (posedge clk) begin
if (!rst_ext_i) begin
jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {`JTAG_RESET_FF_LEVELS{1'b1}};
end if (rst_jtag_i) begin
jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {`JTAG_RESET_FF_LEVELS{1'b0}};
end else begin
jtag_rst_r <= 1'b1;
jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {jtag_rst_r[`JTAG_RESET_FF_LEVELS-2:0], 1'b1};
end
end
assign core_rst_n_o = ext_rst_r & jtag_rst_r;
assign core_rst_n_o = ext_rst_r & jtag_rst_r[`JTAG_RESET_FF_LEVELS-1];
assign jtag_rst_n_o = ext_rst_r;
endmodule

16
rtl/debug/jtag_dm.v
View File

@ -147,7 +147,7 @@ module jtag_dm #(
wire[DMI_DATA_BITS-1:0] data = rx_data_r[DMI_DATA_BITS+DMI_OP_BITS-1:DMI_OP_BITS];
wire[DMI_ADDR_BITS-1:0] address = rx_data_r[DTM_REQ_BITS-1:DMI_DATA_BITS+DMI_OP_BITS];
wire read_dmstatus = (op == `DTM_OP_READ) & (address == DMSTATUS);
wire req_sys_bus = ~(address == DMSTATUS);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
@ -250,6 +250,11 @@ module jtag_dm #(
dm_halt_req <= 1'b1;
// clear ALLRUNNING ANYRUNNING and set ALLHALTED
dmstatus <= {dmstatus[31:12], 4'h3, dmstatus[7:0]};
// reset
end else if (data[1] == 1'b1) begin
dm_reset_req <= 1'b1;
dm_halt_req <= 1'b0;
dmstatus <= {dmstatus[31:12], 4'hc, dmstatus[7:0]};
// resume
end else if (dm_halt_req == 1'b1 && data[30] == 1'b1) begin
dm_halt_req <= 1'b0;
@ -277,12 +282,7 @@ module jtag_dm #(
end
// write
end else begin
// when write dpc, we reset cpu here
if (data[15:0] == DPC) begin
dm_reset_req <= 1'b1;
dm_halt_req <= 1'b0;
dmstatus <= {dmstatus[31:12], 4'hc, dmstatus[7:0]};
end else if (data[15:0] < 16'h1020) begin
if (data[15:0] < 16'h1020) begin
dm_reg_we <= 1'b1;
dm_reg_wdata <= data0;
end
@ -346,7 +346,7 @@ module jtag_dm #(
assign dm_mem_addr_o = dm_mem_addr;
assign dm_mem_wdata_o = dm_mem_wdata;
assign req_valid_o = (state != STATE_IDLE) & (~read_dmstatus);
assign req_valid_o = (state != STATE_IDLE) & req_sys_bus;
assign dm_halt_req_o = dm_halt_req;
assign dm_reset_req_o = dm_reset_req;