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temp commit 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-07-09 15:18:09 +08:00
parent 53e4263706
commit fd2c981317
6 changed files with 52 additions and 45 deletions
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16
rtl/core/csr_reg.sv
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@ -22,7 +22,7 @@ module csr_reg(
input wire clk, input wire clk,
input wire rst_n, input wire rst_n,
// exu // from exu
input wire exu_we_i, // exu模块写寄存器标志 input wire exu_we_i, // exu模块写寄存器标志
input wire[31:0] exu_waddr_i, // exu模块写寄存器地址 input wire[31:0] exu_waddr_i, // exu模块写寄存器地址
input wire[31:0] exu_wdata_i, // exu模块写寄存器数据 input wire[31:0] exu_wdata_i, // exu模块写寄存器数据
@ -32,10 +32,10 @@ module csr_reg(
input wire[31:0] pc_if_i, // 取指地址 input wire[31:0] pc_if_i, // 取指地址
output wire trigger_match_o, // 断点 output wire trigger_match_o, // 断点
// clint // form exception
input wire clint_we_i, // clint模块写寄存器标志 input wire excep_we_i, // exception模块写寄存器标志
input wire[31:0] clint_waddr_i, // clint模块写寄存器地址 input wire[31:0] excep_waddr_i, // exception模块写寄存器地址
input wire[31:0] clint_wdata_i, // clint模块写寄存器数据 input wire[31:0] excep_wdata_i, // exception模块写寄存器数据
output wire[31:0] mtvec_o, // mtvec寄存器值 output wire[31:0] mtvec_o, // mtvec寄存器值
output wire[31:0] mepc_o, // mepc寄存器值 output wire[31:0] mepc_o, // mepc寄存器值
@ -188,9 +188,9 @@ module csr_reg(
assign exu_rdata_o = exu_rdata; assign exu_rdata_o = exu_rdata;
// 写CSR寄存器 // 写CSR寄存器
wire we = exu_we_i | clint_we_i; wire we = exu_we_i | excep_we_i;
wire[31:0] waddr = exu_we_i? exu_waddr_i: clint_waddr_i; wire[31:0] waddr = exu_we_i? exu_waddr_i: excep_waddr_i;
wire[31:0] wdata = exu_we_i? exu_wdata_i: clint_wdata_i; wire[31:0] wdata = exu_we_i? exu_wdata_i: excep_wdata_i;
always @ (*) begin always @ (*) begin
mtvec_d = mtvec_q; mtvec_d = mtvec_q;

65
rtl/core/tinyriscv_core.sv
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@ -20,7 +20,8 @@
module tinyriscv_core #( module tinyriscv_core #(
parameter int unsigned DEBUG_HALT_ADDR = 32'h10000800, parameter int unsigned DEBUG_HALT_ADDR = 32'h10000800,
parameter int unsigned DEBUG_EXCEPTION_ADDR = 32'h10000808, parameter int unsigned DEBUG_EXCEPTION_ADDR = 32'h10000808,
parameter bit BranchPredictor = 1'b1 parameter bit BranchPredictor = 1'b1,
parameter bit TRACE_ENABLE = 1'b0
)( )(
input wire clk, input wire clk,
@ -45,13 +46,13 @@ module tinyriscv_core #(
input wire[31:0] data_rdata_i, input wire[31:0] data_rdata_i,
input wire data_err_i, input wire data_err_i,
// interrupt inputs // interrupt input
input wire irq_software_i, input wire irq_software_i,
input wire irq_timer_i, input wire irq_timer_i,
input wire irq_external_i, input wire irq_external_i,
input wire[14:0] irq_fast_i, input wire[14:0] irq_fast_i,
// debug req signal // debug request signal
input wire debug_req_i input wire debug_req_i
); );
@ -140,13 +141,13 @@ module tinyriscv_core #(
wire ctrl_flush_o; wire ctrl_flush_o;
wire[`STALL_WIDTH-1:0] ctrl_stall_o; wire[`STALL_WIDTH-1:0] ctrl_stall_o;
// clint模块输出信号 // exception模块输出信号
wire clint_csr_we_o; wire excep_csr_we_o;
wire[31:0] clint_csr_waddr_o; wire[31:0] excep_csr_waddr_o;
wire[31:0] clint_csr_wdata_o; wire[31:0] excep_csr_wdata_o;
wire clint_stall_flag_o; wire excep_stall_flag_o;
wire[31:0] clint_int_addr_o; wire[31:0] excep_int_addr_o;
wire clint_int_assert_o; wire excep_int_assert_o;
ifu #( ifu #(
@ -175,7 +176,7 @@ module tinyriscv_core #(
.stall_from_id_i(id_stall_o), .stall_from_id_i(id_stall_o),
.stall_from_ex_i(ex_hold_flag_o), .stall_from_ex_i(ex_hold_flag_o),
.stall_from_jtag_i(1'b0), .stall_from_jtag_i(1'b0),
.stall_from_clint_i(clint_stall_flag_o), .stall_from_clint_i(excep_stall_flag_o),
.jump_assert_i(ex_jump_flag_o), .jump_assert_i(ex_jump_flag_o),
.jump_addr_i(ex_jump_addr_o), .jump_addr_i(ex_jump_addr_o),
.flush_o(ctrl_flush_o), .flush_o(ctrl_flush_o),
@ -205,9 +206,9 @@ module tinyriscv_core #(
.exu_waddr_i(ex_csr_waddr_o), .exu_waddr_i(ex_csr_waddr_o),
.exu_wdata_i(ex_csr_wdata_o), .exu_wdata_i(ex_csr_wdata_o),
.exu_rdata_o(csr_ex_data_o), .exu_rdata_o(csr_ex_data_o),
.clint_we_i(clint_csr_we_o), .excep_we_i(excep_csr_we_o),
.clint_waddr_i(clint_csr_waddr_o), .excep_waddr_i(excep_csr_waddr_o),
.clint_wdata_i(clint_csr_wdata_o), .excep_wdata_i(excep_csr_wdata_o),
.mtvec_o(csr_mtvec_o), .mtvec_o(csr_mtvec_o),
.mepc_o(csr_mepc_o), .mepc_o(csr_mepc_o),
.mstatus_o(csr_mstatus_o), .mstatus_o(csr_mstatus_o),
@ -300,13 +301,13 @@ module tinyriscv_core #(
.hold_flag_o(ex_hold_flag_o), .hold_flag_o(ex_hold_flag_o),
.jump_flag_o(ex_jump_flag_o), .jump_flag_o(ex_jump_flag_o),
.jump_addr_o(ex_jump_addr_o), .jump_addr_o(ex_jump_addr_o),
.int_assert_i(clint_int_assert_o), .int_assert_i(excep_int_assert_o),
.int_addr_i(clint_int_addr_o), .int_addr_i(excep_int_addr_o),
.inst_ecall_o(ex_inst_ecall_o), .inst_ecall_o(ex_inst_ecall_o),
.inst_ebreak_o(ex_inst_ebreak_o), .inst_ebreak_o(ex_inst_ebreak_o),
.inst_mret_o(ex_inst_mret_o), .inst_mret_o(ex_inst_mret_o),
.inst_dret_o(ex_inst_dret_o), .inst_dret_o(ex_inst_dret_o),
.int_stall_i(clint_stall_flag_o), .int_stall_i(excep_stall_flag_o),
.csr_raddr_o(ex_csr_raddr_o), .csr_raddr_o(ex_csr_raddr_o),
.csr_rdata_i(csr_ex_data_o), .csr_rdata_i(csr_ex_data_o),
.csr_wdata_o(ex_csr_wdata_o), .csr_wdata_o(ex_csr_wdata_o),
@ -348,22 +349,22 @@ module tinyriscv_core #(
.irq_fast_i(irq_fast_i), .irq_fast_i(irq_fast_i),
.debug_halt_addr_i(DEBUG_HALT_ADDR), .debug_halt_addr_i(DEBUG_HALT_ADDR),
.debug_req_i(debug_req_i), .debug_req_i(debug_req_i),
.csr_we_o(clint_csr_we_o), .csr_we_o(excep_csr_we_o),
.csr_waddr_o(clint_csr_waddr_o), .csr_waddr_o(excep_csr_waddr_o),
.csr_wdata_o(clint_csr_wdata_o), .csr_wdata_o(excep_csr_wdata_o),
.stall_flag_o(clint_stall_flag_o), .stall_flag_o(excep_stall_flag_o),
.int_addr_o(clint_int_addr_o), .int_addr_o(excep_int_addr_o),
.int_assert_o(clint_int_assert_o) .int_assert_o(excep_int_assert_o)
); );
`ifdef TRACE_ENABLED if (TRACE_ENABLE) begin: instr_trace
tracer u_tracer( tracer u_tracer(
.clk(clk), .clk(clk),
.rst_n(rst_n), .rst_n(rst_n),
.inst_i(ie_inst_o), .inst_i(ie_inst_o),
.pc_i(ie_dec_pc_o), .pc_i(ie_dec_pc_o),
.inst_valid_i(ex_inst_valid_o) .inst_valid_i(ex_inst_valid_o)
); );
`endif end
endmodule endmodule

2
rtl/perips/ram.sv
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@ -30,7 +30,7 @@ module ram #(
); );
wire[31:0] addr = addr_i[31:2]; wire[31:0] addr = {6'h0, addr_i[27:2]};
gen_ram #( gen_ram #(
.DP(DP), .DP(DP),

2
rtl/perips/rom.sv
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@ -30,7 +30,7 @@ module rom #(
); );
wire[31:0] addr = addr_i[31:2]; wire[31:0] addr = {6'h0, addr_i[27:2]};
gen_ram #( gen_ram #(
.DP(DP), .DP(DP),

8
rtl/top/tinyriscv_soc_top.sv
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@ -18,7 +18,9 @@
`include "../debug/jtag_def.sv" `include "../debug/jtag_def.sv"
// tinyriscv soc顶层模块 // tinyriscv soc顶层模块
module tinyriscv_soc_top( module tinyriscv_soc_top #(
parameter bit TRACE_ENABLE = 1'b0
)(
input wire clk_50m_i, // 时钟引脚 input wire clk_50m_i, // 时钟引脚
input wire rst_ext_ni, // 复位引脚，低电平有效 input wire rst_ext_ni, // 复位引脚，低电平有效
@ -113,7 +115,9 @@ module tinyriscv_soc_top(
tinyriscv_core #( tinyriscv_core #(
.DEBUG_HALT_ADDR(`DEBUG_ADDR_BASE + `HaltAddress), .DEBUG_HALT_ADDR(`DEBUG_ADDR_BASE + `HaltAddress),
.DEBUG_EXCEPTION_ADDR(`DEBUG_ADDR_BASE + `ExceptionAddress) .DEBUG_EXCEPTION_ADDR(`DEBUG_ADDR_BASE + `ExceptionAddress),
.BranchPredictor(1'b1),
.TRACE_ENABLE(TRACE_ENABLE)
) u_tinyriscv_core ( ) u_tinyriscv_core (
.clk (clk), .clk (clk),
.rst_n (ndmreset_n), .rst_n (ndmreset_n),

4
sim/tb_top_verilator.sv
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@ -99,7 +99,9 @@ module tb_top_verilator #(
end end
end end
tinyriscv_soc_top u_tinyriscv_soc_top( tinyriscv_soc_top #(
.TRACE_ENABLE(1'b1)
) u_tinyriscv_soc_top (
.clk_50m_i(clk_i), .clk_50m_i(clk_i),
.rst_ext_ni(rst_ni), .rst_ext_ni(rst_ni),
.halted_ind_pin(halted) .halted_ind_pin(halted)