From fd2c9813171e2dd46b49c12e0b2f20b7c697c085 Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Fri, 9 Jul 2021 15:18:09 +0800 Subject: [PATCH] temp commit Signed-off-by: liangkangnan --- rtl/core/csr_reg.sv | 16 ++++----- rtl/core/tinyriscv_core.sv | 65 ++++++++++++++++++------------------ rtl/perips/ram.sv | 2 +- rtl/perips/rom.sv | 2 +- rtl/top/tinyriscv_soc_top.sv | 8 +++-- sim/tb_top_verilator.sv | 4 ++- 6 files changed, 52 insertions(+), 45 deletions(-) diff --git a/rtl/core/csr_reg.sv b/rtl/core/csr_reg.sv index db3973b..0f0df79 100644 --- a/rtl/core/csr_reg.sv +++ b/rtl/core/csr_reg.sv @@ -22,7 +22,7 @@ module csr_reg( input wire clk, input wire rst_n, - // exu + // from exu input wire exu_we_i, // exu模块写寄存器标志 input wire[31:0] exu_waddr_i, // exu模块写寄存器地址 input wire[31:0] exu_wdata_i, // exu模块写寄存器数据 @@ -32,10 +32,10 @@ module csr_reg( input wire[31:0] pc_if_i, // 取指地址 output wire trigger_match_o, // 断点 - // clint - input wire clint_we_i, // clint模块写寄存器标志 - input wire[31:0] clint_waddr_i, // clint模块写寄存器地址 - input wire[31:0] clint_wdata_i, // clint模块写寄存器数据 + // form exception + input wire excep_we_i, // exception模块写寄存器标志 + input wire[31:0] excep_waddr_i, // exception模块写寄存器地址 + input wire[31:0] excep_wdata_i, // exception模块写寄存器数据 output wire[31:0] mtvec_o, // mtvec寄存器值 output wire[31:0] mepc_o, // mepc寄存器值 @@ -188,9 +188,9 @@ module csr_reg( assign exu_rdata_o = exu_rdata; // 写CSR寄存器 - wire we = exu_we_i | clint_we_i; - wire[31:0] waddr = exu_we_i? exu_waddr_i: clint_waddr_i; - wire[31:0] wdata = exu_we_i? exu_wdata_i: clint_wdata_i; + wire we = exu_we_i | excep_we_i; + wire[31:0] waddr = exu_we_i? exu_waddr_i: excep_waddr_i; + wire[31:0] wdata = exu_we_i? exu_wdata_i: excep_wdata_i; always @ (*) begin mtvec_d = mtvec_q; diff --git a/rtl/core/tinyriscv_core.sv b/rtl/core/tinyriscv_core.sv index 6369b69..a09ed0b 100644 --- a/rtl/core/tinyriscv_core.sv +++ b/rtl/core/tinyriscv_core.sv @@ -20,7 +20,8 @@ module tinyriscv_core #( parameter int unsigned DEBUG_HALT_ADDR = 32'h10000800, parameter int unsigned DEBUG_EXCEPTION_ADDR = 32'h10000808, - parameter bit BranchPredictor = 1'b1 + parameter bit BranchPredictor = 1'b1, + parameter bit TRACE_ENABLE = 1'b0 )( input wire clk, @@ -45,13 +46,13 @@ module tinyriscv_core #( input wire[31:0] data_rdata_i, input wire data_err_i, - // interrupt inputs + // interrupt input input wire irq_software_i, input wire irq_timer_i, input wire irq_external_i, input wire[14:0] irq_fast_i, - // debug req signal + // debug request signal input wire debug_req_i ); @@ -140,13 +141,13 @@ module tinyriscv_core #( wire ctrl_flush_o; wire[`STALL_WIDTH-1:0] ctrl_stall_o; - // clint模块输出信号 - wire clint_csr_we_o; - wire[31:0] clint_csr_waddr_o; - wire[31:0] clint_csr_wdata_o; - wire clint_stall_flag_o; - wire[31:0] clint_int_addr_o; - wire clint_int_assert_o; + // exception模块输出信号 + wire excep_csr_we_o; + wire[31:0] excep_csr_waddr_o; + wire[31:0] excep_csr_wdata_o; + wire excep_stall_flag_o; + wire[31:0] excep_int_addr_o; + wire excep_int_assert_o; ifu #( @@ -175,7 +176,7 @@ module tinyriscv_core #( .stall_from_id_i(id_stall_o), .stall_from_ex_i(ex_hold_flag_o), .stall_from_jtag_i(1'b0), - .stall_from_clint_i(clint_stall_flag_o), + .stall_from_clint_i(excep_stall_flag_o), .jump_assert_i(ex_jump_flag_o), .jump_addr_i(ex_jump_addr_o), .flush_o(ctrl_flush_o), @@ -205,9 +206,9 @@ module tinyriscv_core #( .exu_waddr_i(ex_csr_waddr_o), .exu_wdata_i(ex_csr_wdata_o), .exu_rdata_o(csr_ex_data_o), - .clint_we_i(clint_csr_we_o), - .clint_waddr_i(clint_csr_waddr_o), - .clint_wdata_i(clint_csr_wdata_o), + .excep_we_i(excep_csr_we_o), + .excep_waddr_i(excep_csr_waddr_o), + .excep_wdata_i(excep_csr_wdata_o), .mtvec_o(csr_mtvec_o), .mepc_o(csr_mepc_o), .mstatus_o(csr_mstatus_o), @@ -300,13 +301,13 @@ module tinyriscv_core #( .hold_flag_o(ex_hold_flag_o), .jump_flag_o(ex_jump_flag_o), .jump_addr_o(ex_jump_addr_o), - .int_assert_i(clint_int_assert_o), - .int_addr_i(clint_int_addr_o), + .int_assert_i(excep_int_assert_o), + .int_addr_i(excep_int_addr_o), .inst_ecall_o(ex_inst_ecall_o), .inst_ebreak_o(ex_inst_ebreak_o), .inst_mret_o(ex_inst_mret_o), .inst_dret_o(ex_inst_dret_o), - .int_stall_i(clint_stall_flag_o), + .int_stall_i(excep_stall_flag_o), .csr_raddr_o(ex_csr_raddr_o), .csr_rdata_i(csr_ex_data_o), .csr_wdata_o(ex_csr_wdata_o), @@ -348,22 +349,22 @@ module tinyriscv_core #( .irq_fast_i(irq_fast_i), .debug_halt_addr_i(DEBUG_HALT_ADDR), .debug_req_i(debug_req_i), - .csr_we_o(clint_csr_we_o), - .csr_waddr_o(clint_csr_waddr_o), - .csr_wdata_o(clint_csr_wdata_o), - .stall_flag_o(clint_stall_flag_o), - .int_addr_o(clint_int_addr_o), - .int_assert_o(clint_int_assert_o) + .csr_we_o(excep_csr_we_o), + .csr_waddr_o(excep_csr_waddr_o), + .csr_wdata_o(excep_csr_wdata_o), + .stall_flag_o(excep_stall_flag_o), + .int_addr_o(excep_int_addr_o), + .int_assert_o(excep_int_assert_o) ); -`ifdef TRACE_ENABLED - tracer u_tracer( - .clk(clk), - .rst_n(rst_n), - .inst_i(ie_inst_o), - .pc_i(ie_dec_pc_o), - .inst_valid_i(ex_inst_valid_o) - ); -`endif + if (TRACE_ENABLE) begin: instr_trace + tracer u_tracer( + .clk(clk), + .rst_n(rst_n), + .inst_i(ie_inst_o), + .pc_i(ie_dec_pc_o), + .inst_valid_i(ex_inst_valid_o) + ); + end endmodule diff --git a/rtl/perips/ram.sv b/rtl/perips/ram.sv index a96c8a5..a8c6a4d 100644 --- a/rtl/perips/ram.sv +++ b/rtl/perips/ram.sv @@ -30,7 +30,7 @@ module ram #( ); - wire[31:0] addr = addr_i[31:2]; + wire[31:0] addr = {6'h0, addr_i[27:2]}; gen_ram #( .DP(DP), diff --git a/rtl/perips/rom.sv b/rtl/perips/rom.sv index 2978aac..feca24b 100644 --- a/rtl/perips/rom.sv +++ b/rtl/perips/rom.sv @@ -30,7 +30,7 @@ module rom #( ); - wire[31:0] addr = addr_i[31:2]; + wire[31:0] addr = {6'h0, addr_i[27:2]}; gen_ram #( .DP(DP), diff --git a/rtl/top/tinyriscv_soc_top.sv b/rtl/top/tinyriscv_soc_top.sv index d158931..7698319 100644 --- a/rtl/top/tinyriscv_soc_top.sv +++ b/rtl/top/tinyriscv_soc_top.sv @@ -18,7 +18,9 @@ `include "../debug/jtag_def.sv" // tinyriscv soc顶层模块 -module tinyriscv_soc_top( +module tinyriscv_soc_top #( + parameter bit TRACE_ENABLE = 1'b0 + )( input wire clk_50m_i, // 时钟引脚 input wire rst_ext_ni, // 复位引脚，低电平有效 @@ -113,7 +115,9 @@ module tinyriscv_soc_top( tinyriscv_core #( .DEBUG_HALT_ADDR(`DEBUG_ADDR_BASE + `HaltAddress), - .DEBUG_EXCEPTION_ADDR(`DEBUG_ADDR_BASE + `ExceptionAddress) + .DEBUG_EXCEPTION_ADDR(`DEBUG_ADDR_BASE + `ExceptionAddress), + .BranchPredictor(1'b1), + .TRACE_ENABLE(TRACE_ENABLE) ) u_tinyriscv_core ( .clk (clk), .rst_n (ndmreset_n), diff --git a/sim/tb_top_verilator.sv b/sim/tb_top_verilator.sv index fe05d94..8e9816c 100644 --- a/sim/tb_top_verilator.sv +++ b/sim/tb_top_verilator.sv @@ -99,7 +99,9 @@ module tb_top_verilator #( end end - tinyriscv_soc_top u_tinyriscv_soc_top( + tinyriscv_soc_top #( + .TRACE_ENABLE(1'b1) + ) u_tinyriscv_soc_top ( .clk_50m_i(clk_i), .rst_ext_ni(rst_ni), .halted_ind_pin(halted)