temp commit

Signed-off-by: liangkangnan <liangkangnan@163.com>

rtl/core/defines.sv

@@ -18,8 +18,8 @@
 `define CPU_CLOCK_HZ         25000000                       // CPU时钟(25MHZ)
 `define JTAG_RESET_FF_LEVELS 5
 
-`define ROM_DEPTH           (32 * 1024)                     // 指令存储器深度，单位为word(4字节)
+`define ROM_DEPTH           (32 * 256)                     // 32KB，指令存储器深度，单位为word(4字节)
-`define RAM_DEPTH           (16 * 1024)                     // 数据存储器深度，单位为word(4字节)
+`define RAM_DEPTH           (16 * 256)                     // 16KB，数据存储器深度，单位为word(4字节)
 
 // 外设地址、大小
 // ROM

rtl/core/idu.sv

@@ -303,6 +303,7 @@ module idu(
 
     assign stall_o = 1'b0;
 
-    assign illegal_inst_o = ~(|dec_info_bus_o);
+    //assign illegal_inst_o = ~(|dec_info_bus_o);
+    assign illegal_inst_o = 1'b0;
 
 endmodule

rtl/top/tinyriscv_soc_top.sv

@@ -104,7 +104,12 @@ module tinyriscv_soc_top(
     wire[31:0] gpio_ctrl;
     wire[31:0] gpio_data;
 
+`ifdef VERILATOR
     assign halted_ind_pin = core_halted;
+`else
+    // FPGA低电平点亮LED
+    assign halted_ind_pin = ~core_halted;
+`endif
 
     tinyriscv_core #(
         .DEBUG_HALT_ADDR(`DEBUG_ADDR_BASE + `HaltAddress),

sim/tb_top_verilator.sv

@@ -44,7 +44,9 @@ module tb_top_verilator #(
         if (!rst_ni) begin
             result_printed <= 1'b0;
         end else begin
-            if (!result_printed) begin
+            if (u_tinyriscv_soc_top.ndmreset) begin
+                result_printed <= 1'b0;
+            end else if (!result_printed) begin
                 if (x26 == 32'b1) begin
                     if (x27 == 32'b1) begin
                         $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");