From fb461a6176708754960ea3396720a1b6feb4151a Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Tue, 25 May 2021 11:45:53 +0800 Subject: [PATCH] temp commit Signed-off-by: liangkangnan --- rtl/core/defines.sv | 4 ++-- rtl/core/idu.sv | 3 ++- rtl/top/tinyriscv_soc_top.sv | 5 +++++ sim/tb_top_verilator.sv | 4 +++- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/rtl/core/defines.sv b/rtl/core/defines.sv index 5d55581..8262576 100644 --- a/rtl/core/defines.sv +++ b/rtl/core/defines.sv @@ -18,8 +18,8 @@ `define CPU_CLOCK_HZ 25000000 // CPU时钟(25MHZ) `define JTAG_RESET_FF_LEVELS 5 -`define ROM_DEPTH (32 * 1024) // 指令存储器深度,单位为word(4字节) -`define RAM_DEPTH (16 * 1024) // 数据存储器深度,单位为word(4字节) +`define ROM_DEPTH (32 * 256) // 32KB,指令存储器深度,单位为word(4字节) +`define RAM_DEPTH (16 * 256) // 16KB,数据存储器深度,单位为word(4字节) // 外设地址、大小 // ROM diff --git a/rtl/core/idu.sv b/rtl/core/idu.sv index 8e021dd..19a1ea6 100644 --- a/rtl/core/idu.sv +++ b/rtl/core/idu.sv @@ -303,6 +303,7 @@ module idu( assign stall_o = 1'b0; - assign illegal_inst_o = ~(|dec_info_bus_o); + //assign illegal_inst_o = ~(|dec_info_bus_o); + assign illegal_inst_o = 1'b0; endmodule diff --git a/rtl/top/tinyriscv_soc_top.sv b/rtl/top/tinyriscv_soc_top.sv index ab2e48e..cb9ff0a 100644 --- a/rtl/top/tinyriscv_soc_top.sv +++ b/rtl/top/tinyriscv_soc_top.sv @@ -104,7 +104,12 @@ module tinyriscv_soc_top( wire[31:0] gpio_ctrl; wire[31:0] gpio_data; +`ifdef VERILATOR assign halted_ind_pin = core_halted; +`else + // FPGA低电平点亮LED + assign halted_ind_pin = ~core_halted; +`endif tinyriscv_core #( .DEBUG_HALT_ADDR(`DEBUG_ADDR_BASE + `HaltAddress), diff --git a/sim/tb_top_verilator.sv b/sim/tb_top_verilator.sv index 05c64f2..6f16d2d 100644 --- a/sim/tb_top_verilator.sv +++ b/sim/tb_top_verilator.sv @@ -44,7 +44,9 @@ module tb_top_verilator #( if (!rst_ni) begin result_printed <= 1'b0; end else begin - if (!result_printed) begin + if (u_tinyriscv_soc_top.ndmreset) begin + result_printed <= 1'b0; + end else if (!result_printed) begin if (x26 == 32'b1) begin if (x27 == 32'b1) begin $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");