sim: add compliance test script

Signed-off-by: liangkangnan <liangkangnan@163.com>

sim/compliance_test/compliance_test.py

@@ -0,0 +1,125 @@
+import filecmp
+import subprocess
+import sys
+import os
+
+
+# iverilog程序
+iverilog_cmd = ['iverilog']
+# 顶层模块
+#iverilog_cmd += ['-s', r'tinyriscv_soc_tb']
+# 编译生成文件
+iverilog_cmd += ['-o', r'out.vvp']
+# 头文件(defines.v)路径
+iverilog_cmd += ['-I', r'..\..\rtl\core']
+# 宏定义，仿真输出文件
+iverilog_cmd += ['-D', r'OUTPUT="signature.output"']
+# testbench文件
+iverilog_cmd.append(r'..\..\tb\compliance_test\tinyriscv_soc_tb.v')
+# ..\rtl\core
+iverilog_cmd.append(r'..\..\rtl\core\defines.v')
+iverilog_cmd.append(r'..\..\rtl\core\ex.v')
+iverilog_cmd.append(r'..\..\rtl\core\id.v')
+iverilog_cmd.append(r'..\..\rtl\core\tinyriscv.v')
+iverilog_cmd.append(r'..\..\rtl\core\pc_reg.v')
+iverilog_cmd.append(r'..\..\rtl\core\id_ex.v')
+iverilog_cmd.append(r'..\..\rtl\core\ctrl.v')
+iverilog_cmd.append(r'..\..\rtl\core\regs.v')
+iverilog_cmd.append(r'..\..\rtl\core\if_id.v')
+iverilog_cmd.append(r'..\..\rtl\core\div.v')
+iverilog_cmd.append(r'..\..\rtl\core\rib.v')
+iverilog_cmd.append(r'..\..\rtl\core\clint.v')
+iverilog_cmd.append(r'..\..\rtl\core\csr_reg.v')
+# ..\rtl\perips
+iverilog_cmd.append(r'..\..\rtl\perips\ram.v')
+iverilog_cmd.append(r'..\..\rtl\perips\rom.v')
+iverilog_cmd.append(r'..\..\rtl\perips\spi.v')
+iverilog_cmd.append(r'..\..\rtl\perips\timer.v')
+iverilog_cmd.append(r'..\..\rtl\perips\uart_tx.v')
+iverilog_cmd.append(r'..\..\rtl\perips\gpio.v')
+# ..\rtl\debug
+iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v')
+iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v')
+iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v')
+# ..\rtl\soc
+iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')
+
+
+
+# 找出path目录下的所有reference_output文件
+def list_ref_files(path):
+    files = []
+    list_dir = os.walk(path)
+    for maindir, subdir, all_file in list_dir:
+        for filename in all_file:
+            apath = os.path.join(maindir, filename)
+            if apath.endswith('.reference_output'):
+                files.append(apath)
+
+    return files
+
+# 根据bin文件找到对应的reference_output文件
+def get_reference_file(bin_file):
+    file_path, file_name = os.path.split(bin_file)
+    tmp = file_name.split('.')
+    # 得到bin文件的前缀部分
+    prefix = tmp[0]
+    #print('bin prefix: %s' % prefix)
+
+    files = []
+    if (bin_file.find('rv32i') != -1):
+        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32i\references')
+    elif (bin_file.find('rv32im') != -1):
+        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32im\references')
+    elif (bin_file.find('rv32Zicsr') != -1):
+        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zicsr\references')
+    elif (bin_file.find('rv32Zifencei') != -1):
+        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zifencei\references')
+    else:
+        return None
+
+    # 根据bin文件前缀找到对应的reference_output文件
+    for file in files:
+        if (file.find(prefix) != -1):
+            return file
+
+    return None
+
+# 主函数
+def main():
+    #print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
+
+    # 1.将bin文件转成mem文件
+    bin_to_mem_cmd = [r'..\..\tools\BinToMem_CLI.exe']
+    bin_to_mem_cmd.append(sys.argv[1])
+    bin_to_mem_cmd.append(sys.argv[2])
+    process = subprocess.Popen(bin_to_mem_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+    process.wait(timeout=2)
+
+    # 2.编译rtl文件
+    logfile = open('complie.log', 'w')
+    process = subprocess.Popen(iverilog_cmd, stdout=logfile, stderr=logfile)
+    process.wait(timeout=2)
+    logfile.close()
+
+    # 3.运行
+    logfile = open('run.log', 'w')
+    vvp_cmd = [r'vvp']
+    vvp_cmd.append(r'out.vvp')
+    process = subprocess.Popen(vvp_cmd, stdout=logfile, stderr=logfile)
+    process.wait(timeout=2)
+    logfile.close()
+
+    # 4.比较结果
+    ref_file = get_reference_file(sys.argv[1])
+    if (ref_file != None):
+        if (filecmp.cmp('signature.output', ref_file, shallow=False) == True):
+            print('### PASS ###')
+        else:
+            print('!!! FAIL !!!')
+    else:
+        print('No ref file found, please check result by yourself.')
+
+
+if __name__ == '__main__':
+    sys.exit(main())

sim/compliance_test/run.log

@@ -0,0 +1,3 @@
+test running...
+WARNING: ..\..\tb\compliance_test\tinyriscv_soc_tb.v:502: $readmemh(inst.data): Not enough words in the file for the requested range [0:4095].
+VCD info: dumpfile tinyriscv_soc_tb.vcd opened for output.

sim/compliance_test/signature.output

@@ -0,0 +1,36 @@
+00000000
+fffff802
+ffffffff
+fffff5cb
+80000000
+00001a34
+07654320
+80000000
+80000000
+07654320
+00001a34
+80000000
+fffff5cb
+fffffffe
+fffff802
+00000000
+ffffffff
+fffff802
+ffffffff
+fffff5cb
+80000000
+00001a34
+07654320
+80000000
+80000000
+07654320
+00001a34
+80000000
+fffff5cb
+fffffffe
+fffff802
+00000000
+ffffffff
+ffffffff
+ffffffff
+00000000