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rtl:utils:edge_detect: add DP parameter 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-09-01 14:14:36 +08:00
parent 574708bd89
commit f74f2d8f5d
1 changed files with 4 additions and 2 deletions
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6
rtl/utils/edge_detect.sv
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@ -15,7 +15,9 @@
*/ */
// 上升沿、下降沿检测 // 上升沿、下降沿检测
module edge_detect ( module edge_detect #(
parameter int DP = 2
)(
input logic clk_i, input logic clk_i,
input logic rst_ni, input logic rst_ni,
input logic sig_i, input logic sig_i,
@ -39,7 +41,7 @@ module edge_detect (
end end
gen_ticks_sync #( gen_ticks_sync #(
.DP(2), .DP(DP),
.DW(1) .DW(1)
) u_sync ( ) u_sync (
.clk(clk_i), .clk(clk_i),