use = instead of <=

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-05-31 14:38:57 +08:00
parent 1dea4a0a5e
commit eec414aa96
2 changed files with 20 additions and 20 deletions

View File

@ -170,32 +170,32 @@ module csr_reg(
// clintCSR // clintCSR
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
clint_data_o <= `ZeroWord; clint_data_o = `ZeroWord;
end else begin end else begin
case (clint_raddr_i[11:0]) case (clint_raddr_i[11:0])
`CSR_CYCLE: begin `CSR_CYCLE: begin
clint_data_o <= cycle[31:0]; clint_data_o = cycle[31:0];
end end
`CSR_CYCLEH: begin `CSR_CYCLEH: begin
clint_data_o <= cycle[63:32]; clint_data_o = cycle[63:32];
end end
`CSR_MTVEC: begin `CSR_MTVEC: begin
clint_data_o <= mtvec; clint_data_o = mtvec;
end end
`CSR_MCAUSE: begin `CSR_MCAUSE: begin
clint_data_o <= mcause; clint_data_o = mcause;
end end
`CSR_MEPC: begin `CSR_MEPC: begin
clint_data_o <= mepc; clint_data_o = mepc;
end end
`CSR_MIE: begin `CSR_MIE: begin
clint_data_o <= mie; clint_data_o = mie;
end end
`CSR_MSTATUS: begin `CSR_MSTATUS: begin
clint_data_o <= mstatus; clint_data_o = mstatus;
end end
default: begin default: begin
clint_data_o <= `ZeroWord; clint_data_o = `ZeroWord;
end end
endcase endcase
end end

View File

@ -66,39 +66,39 @@ module regs(
// 1 // 1
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
rdata1_o <= `ZeroWord; rdata1_o = `ZeroWord;
end else if (raddr1_i == `RegNumLog2'h0) begin end else if (raddr1_i == `RegNumLog2'h0) begin
rdata1_o <= `ZeroWord; rdata1_o = `ZeroWord;
// //
end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin
rdata1_o <= wdata_i; rdata1_o = wdata_i;
end else begin end else begin
rdata1_o <= regs[raddr1_i]; rdata1_o = regs[raddr1_i];
end end
end end
// 2 // 2
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
rdata2_o <= `ZeroWord; rdata2_o = `ZeroWord;
end else if (raddr2_i == `RegNumLog2'h0) begin end else if (raddr2_i == `RegNumLog2'h0) begin
rdata2_o <= `ZeroWord; rdata2_o = `ZeroWord;
// //
end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin
rdata2_o <= wdata_i; rdata2_o = wdata_i;
end else begin end else begin
rdata2_o <= regs[raddr2_i]; rdata2_o = regs[raddr2_i];
end end
end end
// jtag // jtag
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
jtag_data_o <= `ZeroWord; jtag_data_o = `ZeroWord;
end else if (jtag_addr_i == `RegNumLog2'h0) begin end else if (jtag_addr_i == `RegNumLog2'h0) begin
jtag_data_o <= `ZeroWord; jtag_data_o = `ZeroWord;
end else begin end else begin
jtag_data_o <= regs[jtag_addr_i]; jtag_data_o = regs[jtag_addr_i];
end end
end end