From eec414aa96528809820ca6021ad9ae78c24381f8 Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Sun, 31 May 2020 14:38:57 +0800
Subject: [PATCH] use = instead of <=

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 rtl/core/csr_reg.v | 18 +++++++++---------
 rtl/core/regs.v    | 22 +++++++++++-----------
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/rtl/core/csr_reg.v b/rtl/core/csr_reg.v
index 1c41503..5a5254b 100644
--- a/rtl/core/csr_reg.v
+++ b/rtl/core/csr_reg.v
@@ -170,32 +170,32 @@ module csr_reg(
     // clint模块读CSR寄存器
     always @ (*) begin
         if (rst == `RstEnable) begin
-            clint_data_o <= `ZeroWord;
+            clint_data_o = `ZeroWord;
         end else begin
             case (clint_raddr_i[11:0])
                 `CSR_CYCLE: begin
-                    clint_data_o <= cycle[31:0];
+                    clint_data_o = cycle[31:0];
                 end
                 `CSR_CYCLEH: begin
-                    clint_data_o <= cycle[63:32];
+                    clint_data_o = cycle[63:32];
                 end
                 `CSR_MTVEC: begin
-                    clint_data_o <= mtvec;
+                    clint_data_o = mtvec;
                 end
                 `CSR_MCAUSE: begin
-                    clint_data_o <= mcause;
+                    clint_data_o = mcause;
                 end
                 `CSR_MEPC: begin
-                    clint_data_o <= mepc;
+                    clint_data_o = mepc;
                 end
                 `CSR_MIE: begin
-                    clint_data_o <= mie;
+                    clint_data_o = mie;
                 end
                 `CSR_MSTATUS: begin
-                    clint_data_o <= mstatus;
+                    clint_data_o = mstatus;
                 end
                 default: begin
-                    clint_data_o <= `ZeroWord;
+                    clint_data_o = `ZeroWord;
                 end
             endcase
         end
diff --git a/rtl/core/regs.v b/rtl/core/regs.v
index 5bc0a39..f3a550c 100644
--- a/rtl/core/regs.v
+++ b/rtl/core/regs.v
@@ -66,39 +66,39 @@ module regs(
     // 读寄存器1
     always @ (*) begin
         if (rst == `RstEnable) begin
-            rdata1_o <= `ZeroWord;
+            rdata1_o = `ZeroWord;
         end else if (raddr1_i == `RegNumLog2'h0) begin
-            rdata1_o <= `ZeroWord;
+            rdata1_o = `ZeroWord;
         // 如果读地址等于写地址，并且正在写操作，则直接返回写数据
         end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin
-            rdata1_o <= wdata_i;
+            rdata1_o = wdata_i;
         end else begin
-            rdata1_o <= regs[raddr1_i];
+            rdata1_o = regs[raddr1_i];
         end
     end
 
     // 读寄存器2
     always @ (*) begin
         if (rst == `RstEnable) begin
-            rdata2_o <= `ZeroWord;
+            rdata2_o = `ZeroWord;
         end else if (raddr2_i == `RegNumLog2'h0) begin
-            rdata2_o <= `ZeroWord;
+            rdata2_o = `ZeroWord;
         // 如果读地址等于写地址，并且正在写操作，则直接返回写数据
         end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin
-            rdata2_o <= wdata_i;
+            rdata2_o = wdata_i;
         end else begin
-            rdata2_o <= regs[raddr2_i];
+            rdata2_o = regs[raddr2_i];
         end
     end
 
     // jtag读寄存器
     always @ (*) begin
         if (rst == `RstEnable) begin
-            jtag_data_o <= `ZeroWord;
+            jtag_data_o = `ZeroWord;
         end else if (jtag_addr_i == `RegNumLog2'h0) begin
-            jtag_data_o <= `ZeroWord;
+            jtag_data_o = `ZeroWord;
         end else begin
-            jtag_data_o <= regs[jtag_addr_i];
+            jtag_data_o = regs[jtag_addr_i];
         end
     end