From eb65d0badc14358ac82f23b341be453f4505763e Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Sun, 24 May 2020 13:37:45 +0800
Subject: [PATCH] FPGA: update simulation settings

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 FPGA/README.md | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/FPGA/README.md b/FPGA/README.md
index dc4363b..ea3e396 100644
--- a/FPGA/README.md
+++ b/FPGA/README.md
@@ -166,4 +166,13 @@
 
 ![defines](./images/defines.png)
 
+最后，还要指定inst.data文件的路径，即修改tinyriscv_soc_tb.v文件里的下面这一行：
+
+```
+    // read mem data
+    initial begin
+        $readmemh ("F://yourpath/inst.data", tinyriscv_soc_top_0.u_rom._rom);
+    end
+```
+
 设置完成后，即可进行RTL仿真。
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